;--------------------------------------------------------
; File Created by SDCC : FreeWare ANSI-C Compiler
; Version 2.6.1 #4330 (Oct 18 2006)
; This file generated Wed Oct 18 23:31:20 2006
;--------------------------------------------------------
	.module _strstr
	.optsdcc -mhc08
	
	.area HOME (CODE)
	.area GSINIT0 (CODE)
	.area GSINIT (CODE)
	.area GSFINAL (CODE)
	.area CSEG (CODE)
	.area XINIT
	.area CONST   (CODE)
	.area DSEG
	.area OSEG    (OVR)
	.area BSEG
	.area XSEG
	.area XISEG
;--------------------------------------------------------
; Public variables in this module
;--------------------------------------------------------
	.globl _strstr_PARM_2
	.globl _strstr
;--------------------------------------------------------
;  ram data
;--------------------------------------------------------
	.area DSEG
;--------------------------------------------------------
; overlayable items in  ram 
;--------------------------------------------------------
	.area	OSEG    (OVR)
_strstr_sloc0_1_0::
	.ds 2
_strstr_sloc1_1_0::
	.ds 2
_strstr_sloc2_1_0::
	.ds 2
_strstr_sloc3_1_0::
	.ds 2
_strstr_sloc4_1_0::
	.ds 1
;--------------------------------------------------------
; external initialized ram data
;--------------------------------------------------------
	.area XISEG
;--------------------------------------------------------
; extended address mode data
;--------------------------------------------------------
	.area XSEG
_strstr_PARM_2:
	.ds 2
_strstr_str1_1_1:
	.ds 2
_strstr_cp_1_1:
	.ds 2
_strstr_s2_1_1:
	.ds 2
;--------------------------------------------------------
; global & static initialisations
;--------------------------------------------------------
	.area HOME (CODE)
	.area GSINIT (CODE)
	.area GSFINAL (CODE)
	.area GSINIT (CODE)
;--------------------------------------------------------
; Home
;--------------------------------------------------------
	.area HOME (CODE)
	.area CSEG (CODE)
;--------------------------------------------------------
; code
;--------------------------------------------------------
	.area CSEG (CODE)
;------------------------------------------------------------
;Allocation info for local variables in function 'strstr'
;------------------------------------------------------------
;str2                      Allocated with name '_strstr_PARM_2'
;str1                      Allocated with name '_strstr_str1_1_1'
;cp                        Allocated with name '_strstr_cp_1_1'
;s1                        Allocated to registers 
;s2                        Allocated with name '_strstr_s2_1_1'
;sloc0                     Allocated with name '_strstr_sloc0_1_0'
;sloc1                     Allocated with name '_strstr_sloc1_1_0'
;sloc2                     Allocated with name '_strstr_sloc2_1_0'
;sloc3                     Allocated with name '_strstr_sloc3_1_0'
;sloc4                     Allocated with name '_strstr_sloc4_1_0'
;------------------------------------------------------------
;_strstr.c:26: char * strstr (
;	-----------------------------------------
;	 function strstr
;	-----------------------------------------
_strstr:
;     genReceive
;     loadRegFromAop (a, REG(-,-,-,a), 0)
; transferRegReg(a,a)
;     storeRegToAop (a, EXT(_strstr_str1_1_1), 0), stacked=0, isaddr=0
	sta	(_strstr_str1_1_1 + 1)
;     loadRegFromAop (x, REG(-,-,-,x), 0)
; transferRegReg(x,x)
;     storeRegToAop (x, EXT(_strstr_str1_1_1), 1), stacked=0, isaddr=0
	stx	_strstr_str1_1_1
;_strstr.c:31: char * cp = str1;
;     genAssign
;     loadRegFromAop (a, EXT(_strstr_str1_1_1), 1)
	lda	_strstr_str1_1_1
;     storeRegToAop (a, EXT(_strstr_cp_1_1), 1), stacked=0, isaddr=0
	sta	_strstr_cp_1_1
;     loadRegFromAop (a, EXT(_strstr_str1_1_1), 0)
	lda	(_strstr_str1_1_1 + 1)
;     storeRegToAop (a, EXT(_strstr_cp_1_1), 0), stacked=0, isaddr=0
	sta	(_strstr_cp_1_1 + 1)
;_strstr.c:35: if ( !*str2 )
;     genAssign
;     loadRegFromAop (a, EXT(_strstr_PARM_2), 1)
	lda	_strstr_PARM_2
;     storeRegToAop (a, DIR(_strstr_sloc0_1_0), 1), stacked=0, isaddr=0
	sta	*_strstr_sloc0_1_0
;     loadRegFromAop (a, EXT(_strstr_PARM_2), 0)
	lda	(_strstr_PARM_2 + 1)
;     storeRegToAop (a, DIR(_strstr_sloc0_1_0), 0), stacked=0, isaddr=0
	sta	*(_strstr_sloc0_1_0 + 1)
;     genPointerGet
;     loadRegFromAop (hx, DIR(_strstr_sloc0_1_0), 0)
	ldhx	*_strstr_sloc0_1_0
	lda	,x
;     genIfxJump
; Peephole 2c	- eliminated jmp
	bne	00122$
00124$:
;_strstr.c:36: return str1;
;     genRet
;     loadRegFromAop (x, EXT(_strstr_str1_1_1), 1)
	ldx	_strstr_str1_1_1
;     storeRegToAop (x, REG(-,-,-,x), 0), stacked=0, isaddr=0
; transferRegReg(x,x)
;     loadRegFromAop (a, EXT(_strstr_str1_1_1), 0)
	lda	(_strstr_str1_1_1 + 1)
;     storeRegToAop (a, REG(-,-,-,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
; Peephole 6a  - replaced jmp to rts with rts
	rts
;_strstr.c:38: while (*cp)
00122$:
;     genAssign
;     loadRegFromAop (a, EXT(_strstr_str1_1_1), 1)
	lda	_strstr_str1_1_1
;     storeRegToAop (a, DIR(_strstr_sloc1_1_0), 1), stacked=0, isaddr=0
	sta	*_strstr_sloc1_1_0
;     loadRegFromAop (a, EXT(_strstr_str1_1_1), 0)
	lda	(_strstr_str1_1_1 + 1)
;     storeRegToAop (a, DIR(_strstr_sloc1_1_0), 0), stacked=0, isaddr=0
	sta	*(_strstr_sloc1_1_0 + 1)
00110$:
;     genPointerGet
;     loadRegFromAop (hx, DIR(_strstr_sloc1_1_0), 0)
	ldhx	*_strstr_sloc1_1_0
	lda	,x
;     genIfxJump
	bne	00125$
	jmp	00112$
00125$:
;_strstr.c:41: s2 = str2;
;     genAssign
;     loadRegFromAop (a, DIR(_strstr_sloc0_1_0), 1)
	lda	*_strstr_sloc0_1_0
;     storeRegToAop (a, EXT(_strstr_s2_1_1), 1), stacked=0, isaddr=0
	sta	_strstr_s2_1_1
;     loadRegFromAop (a, DIR(_strstr_sloc0_1_0), 0)
	lda	*(_strstr_sloc0_1_0 + 1)
;     storeRegToAop (a, EXT(_strstr_s2_1_1), 0), stacked=0, isaddr=0
	sta	(_strstr_s2_1_1 + 1)
;_strstr.c:43: while ( *s1 && *s2 && !(*s1-*s2) )
;     genAssign
	mov	*_strstr_sloc1_1_0,*_strstr_sloc2_1_0
	mov	*(_strstr_sloc1_1_0 + 1),*(_strstr_sloc2_1_0 + 1)
;     genAssign
;     loadRegFromAop (a, EXT(_strstr_s2_1_1), 1)
	lda	_strstr_s2_1_1
;     storeRegToAop (a, DIR(_strstr_sloc3_1_0), 1), stacked=0, isaddr=0
	sta	*_strstr_sloc3_1_0
;     loadRegFromAop (a, EXT(_strstr_s2_1_1), 0)
	lda	(_strstr_s2_1_1 + 1)
;     storeRegToAop (a, DIR(_strstr_sloc3_1_0), 0), stacked=0, isaddr=0
	sta	*(_strstr_sloc3_1_0 + 1)
00105$:
;     genPointerGet
;     loadRegFromAop (hx, DIR(_strstr_sloc2_1_0), 0)
	ldhx	*_strstr_sloc2_1_0
	lda	,x
;     genIfxJump
; Peephole 2d	- eliminated jmp
	beq	00107$
00126$:
;     genPointerGet
;     loadRegFromAop (hx, DIR(_strstr_sloc3_1_0), 0)
	ldhx	*_strstr_sloc3_1_0
	lda	,x
;     genIfxJump
; Peephole 2d	- eliminated jmp
	beq	00107$
00127$:
;     genPointerGet
;     loadRegFromAop (hx, DIR(_strstr_sloc2_1_0), 0)
	ldhx	*_strstr_sloc2_1_0
	lda	,x
;     storeRegToAop (a, DIR(_strstr_sloc4_1_0), 0), stacked=0, isaddr=0
	sta	*_strstr_sloc4_1_0
;     genPointerGet
;     loadRegFromAop (hx, DIR(_strstr_sloc3_1_0), 0)
	ldhx	*_strstr_sloc3_1_0
	lda	,x
;     storeRegToAop (a, REG(-,-,x,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
;     genDjnz
;     genMinus
;     loadRegFromAop (a, REG(-,-,x,a), 0)
; transferRegReg(a,a)
	sub	*_strstr_sloc4_1_0
	nega	
;     storeRegToAop (a, REG(-,-,x,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
; forgot to free a
;     genIfx
	tsta
;     genIfxJump
; Peephole 2c	- eliminated jmp
	bne	00107$
00128$:
; forgot to free a
;_strstr.c:44: s1++, s2++;
; checking lic
; checking IS_ITEMP
; pset=0, pget=0
;     genPlus
; IS_AOP_HX = 0
;     loadRegFromAop (hx, DIR(_strstr_sloc2_1_0), 0)
	ldhx	*_strstr_sloc2_1_0
	aix	#1
;     storeRegToAop (hx, DIR(_strstr_sloc2_1_0), 0), stacked=0, isaddr=0
	sthx	*_strstr_sloc2_1_0
; checking lic
; checking IS_ITEMP
; pset=0, pget=0
;     genPlus
; IS_AOP_HX = 0
;     loadRegFromAop (hx, DIR(_strstr_sloc3_1_0), 0)
	ldhx	*_strstr_sloc3_1_0
	aix	#1
;     storeRegToAop (hx, DIR(_strstr_sloc3_1_0), 0), stacked=0, isaddr=0
	sthx	*_strstr_sloc3_1_0
; Peephole 3	- shortened jmp to bra
	bra	00105$
00107$:
;_strstr.c:46: if (!*s2)
;     genPointerGet
;     loadRegFromAop (hx, DIR(_strstr_sloc3_1_0), 0)
	ldhx	*_strstr_sloc3_1_0
	lda	,x
;     genIfxJump
; Peephole 2c	- eliminated jmp
	bne	00109$
00129$:
;_strstr.c:47: return(cp);
;     genRet
;     loadRegFromAop (x, EXT(_strstr_cp_1_1), 1)
	ldx	_strstr_cp_1_1
;     storeRegToAop (x, REG(-,-,-,x), 0), stacked=0, isaddr=0
; transferRegReg(x,x)
;     loadRegFromAop (a, EXT(_strstr_cp_1_1), 0)
	lda	(_strstr_cp_1_1 + 1)
;     storeRegToAop (a, REG(-,-,-,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
; Peephole 3	- shortened jmp to bra
; Peephole 6b  - replaced jmp to rts with rts
	rts
00109$:
;_strstr.c:49: cp++;
; checking lic
; checking IS_ITEMP
; pset=0, pget=0
;     genPlus
; IS_AOP_HX = 0
;     loadRegFromAop (hx, DIR(_strstr_sloc1_1_0), 0)
	ldhx	*_strstr_sloc1_1_0
	aix	#1
;     storeRegToAop (hx, DIR(_strstr_sloc1_1_0), 0), stacked=0, isaddr=0
	sthx	*_strstr_sloc1_1_0
;     genAssign
;     loadRegFromAop (a, DIR(_strstr_sloc1_1_0), 1)
	lda	*_strstr_sloc1_1_0
;     storeRegToAop (a, EXT(_strstr_cp_1_1), 1), stacked=0, isaddr=0
	sta	_strstr_cp_1_1
;     loadRegFromAop (a, DIR(_strstr_sloc1_1_0), 0)
	lda	*(_strstr_sloc1_1_0 + 1)
;     storeRegToAop (a, EXT(_strstr_cp_1_1), 0), stacked=0, isaddr=0
	sta	(_strstr_cp_1_1 + 1)
	jmp	00110$
00112$:
;_strstr.c:52: return (NULL) ;
;     genRet
;     loadRegFromAop (x, LIT(#0x00), 1)
	clrx
;     storeRegToAop (x, REG(-,-,-,x), 0), stacked=0, isaddr=0
; transferRegReg(x,x)
;     loadRegFromAop (a, LIT(#0x00), 0)
	clra
;     storeRegToAop (a, REG(-,-,-,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
00113$:
	rts
	.area CSEG (CODE)
	.area CONST   (CODE)
	.area XINIT
