;--------------------------------------------------------
; File Created by SDCC : FreeWare ANSI-C Compiler
; Version 2.6.1 #4330 (Oct 18 2006)
; This file generated Wed Oct 18 23:31:20 2006
;--------------------------------------------------------
	.module _strncmp
	.optsdcc -mhc08
	
	.area HOME (CODE)
	.area GSINIT0 (CODE)
	.area GSINIT (CODE)
	.area GSFINAL (CODE)
	.area CSEG (CODE)
	.area XINIT
	.area CONST   (CODE)
	.area DSEG
	.area OSEG    (OVR)
	.area BSEG
	.area XSEG
	.area XISEG
;--------------------------------------------------------
; Public variables in this module
;--------------------------------------------------------
	.globl _strncmp_PARM_3
	.globl _strncmp_PARM_2
	.globl _strncmp
;--------------------------------------------------------
;  ram data
;--------------------------------------------------------
	.area DSEG
;--------------------------------------------------------
; overlayable items in  ram 
;--------------------------------------------------------
	.area	OSEG    (OVR)
_strncmp_sloc0_1_0::
	.ds 2
_strncmp_sloc1_1_0::
	.ds 2
_strncmp_sloc2_1_0::
	.ds 2
_strncmp_sloc3_1_0::
	.ds 1
;--------------------------------------------------------
; external initialized ram data
;--------------------------------------------------------
	.area XISEG
;--------------------------------------------------------
; extended address mode data
;--------------------------------------------------------
	.area XSEG
_strncmp_PARM_2:
	.ds 2
_strncmp_PARM_3:
	.ds 2
_strncmp_first_1_1:
	.ds 2
;--------------------------------------------------------
; global & static initialisations
;--------------------------------------------------------
	.area HOME (CODE)
	.area GSINIT (CODE)
	.area GSFINAL (CODE)
	.area GSINIT (CODE)
;--------------------------------------------------------
; Home
;--------------------------------------------------------
	.area HOME (CODE)
	.area CSEG (CODE)
;--------------------------------------------------------
; code
;--------------------------------------------------------
	.area CSEG (CODE)
;------------------------------------------------------------
;Allocation info for local variables in function 'strncmp'
;------------------------------------------------------------
;last                      Allocated with name '_strncmp_PARM_2'
;count                     Allocated with name '_strncmp_PARM_3'
;first                     Allocated with name '_strncmp_first_1_1'
;sloc0                     Allocated with name '_strncmp_sloc0_1_0'
;sloc1                     Allocated with name '_strncmp_sloc1_1_0'
;sloc2                     Allocated with name '_strncmp_sloc2_1_0'
;sloc3                     Allocated with name '_strncmp_sloc3_1_0'
;------------------------------------------------------------
;_strncmp.c:26: int strncmp (
;	-----------------------------------------
;	 function strncmp
;	-----------------------------------------
_strncmp:
;     genReceive
;     loadRegFromAop (a, REG(-,-,-,a), 0)
; transferRegReg(a,a)
;     storeRegToAop (a, EXT(_strncmp_first_1_1), 0), stacked=0, isaddr=0
	sta	(_strncmp_first_1_1 + 1)
;     loadRegFromAop (x, REG(-,-,-,x), 0)
; transferRegReg(x,x)
;     storeRegToAop (x, EXT(_strncmp_first_1_1), 1), stacked=0, isaddr=0
	stx	_strncmp_first_1_1
;_strncmp.c:32: if (!count)
;     genIfx
;     loadRegFromAop (a, EXT(_strncmp_PARM_3), 0)
	lda	(_strncmp_PARM_3 + 1)
	ora	_strncmp_PARM_3
;     genIfxJump
; Peephole 2c	- eliminated jmp
	bne	00114$
00116$:
;_strncmp.c:33: return(0);
;     genRet
;     loadRegFromAop (x, LIT(#0x00), 1)
	clrx
;     storeRegToAop (x, REG(-,-,-,x), 0), stacked=0, isaddr=0
; transferRegReg(x,x)
;     loadRegFromAop (a, LIT(#0x00), 0)
	clra
;     storeRegToAop (a, REG(-,-,-,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
; Peephole 6a  - replaced jmp to rts with rts
	rts
;_strncmp.c:35: while (--count && *first && *first == *last) {
00114$:
;     genAssign
;     loadRegFromAop (a, EXT(_strncmp_first_1_1), 1)
	lda	_strncmp_first_1_1
;     storeRegToAop (a, DIR(_strncmp_sloc0_1_0), 1), stacked=0, isaddr=0
	sta	*_strncmp_sloc0_1_0
;     loadRegFromAop (a, EXT(_strncmp_first_1_1), 0)
	lda	(_strncmp_first_1_1 + 1)
;     storeRegToAop (a, DIR(_strncmp_sloc0_1_0), 0), stacked=0, isaddr=0
	sta	*(_strncmp_sloc0_1_0 + 1)
;     genAssign
;     loadRegFromAop (a, EXT(_strncmp_PARM_2), 1)
	lda	_strncmp_PARM_2
;     storeRegToAop (a, DIR(_strncmp_sloc1_1_0), 1), stacked=0, isaddr=0
	sta	*_strncmp_sloc1_1_0
;     loadRegFromAop (a, EXT(_strncmp_PARM_2), 0)
	lda	(_strncmp_PARM_2 + 1)
;     storeRegToAop (a, DIR(_strncmp_sloc1_1_0), 0), stacked=0, isaddr=0
	sta	*(_strncmp_sloc1_1_0 + 1)
;     genAssign
;     loadRegFromAop (a, EXT(_strncmp_PARM_3), 1)
	lda	_strncmp_PARM_3
;     storeRegToAop (a, DIR(_strncmp_sloc2_1_0), 1), stacked=0, isaddr=0
	sta	*_strncmp_sloc2_1_0
;     loadRegFromAop (a, EXT(_strncmp_PARM_3), 0)
	lda	(_strncmp_PARM_3 + 1)
;     storeRegToAop (a, DIR(_strncmp_sloc2_1_0), 0), stacked=0, isaddr=0
	sta	*(_strncmp_sloc2_1_0 + 1)
00105$:
;     genMinus
;     loadRegFromAop (a, DIR(_strncmp_sloc2_1_0), 0)
	lda	*(_strncmp_sloc2_1_0 + 1)
	sub	#0x01
;     storeRegToAop (a, DIR(_strncmp_sloc2_1_0), 0), stacked=0, isaddr=0
	sta	*(_strncmp_sloc2_1_0 + 1)
;     loadRegFromAop (a, DIR(_strncmp_sloc2_1_0), 1)
	lda	*_strncmp_sloc2_1_0
	sbc	#0x00
;     storeRegToAop (a, DIR(_strncmp_sloc2_1_0), 1), stacked=0, isaddr=0
	sta	*_strncmp_sloc2_1_0
;     genIfx
;     loadRegFromAop (a, DIR(_strncmp_sloc2_1_0), 0)
	lda	*(_strncmp_sloc2_1_0 + 1)
	ora	*_strncmp_sloc2_1_0
;     genIfxJump
; Peephole 2d	- eliminated jmp
	beq	00107$
00117$:
;     genPointerGet
;     loadRegFromAop (hx, DIR(_strncmp_sloc0_1_0), 0)
	ldhx	*_strncmp_sloc0_1_0
	lda	,x
;     genIfxJump
; Peephole 2d	- eliminated jmp
	beq	00107$
00118$:
;     genPointerGet
;     loadRegFromAop (hx, DIR(_strncmp_sloc0_1_0), 0)
	ldhx	*_strncmp_sloc0_1_0
	lda	,x
;     storeRegToAop (a, DIR(_strncmp_sloc3_1_0), 0), stacked=0, isaddr=0
	sta	*_strncmp_sloc3_1_0
;     genPointerGet
;     loadRegFromAop (hx, DIR(_strncmp_sloc1_1_0), 0)
	ldhx	*_strncmp_sloc1_1_0
	lda	,x
;     storeRegToAop (a, REG(-,-,x,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
;     genCmpEQorNE	(==)
;     loadRegFromAop (a, REG(-,-,x,a), 0)
; transferRegReg(a,a)
	cmp	*_strncmp_sloc3_1_0
; Peephole 2c	- eliminated jmp
	bne	00107$
00119$:
;_strncmp.c:36: first++;
; checking lic
; checking IS_ITEMP
; pset=0, pget=0
;     genPlus
; IS_AOP_HX = 0
;     loadRegFromAop (hx, DIR(_strncmp_sloc0_1_0), 0)
	ldhx	*_strncmp_sloc0_1_0
	aix	#1
;     storeRegToAop (hx, DIR(_strncmp_sloc0_1_0), 0), stacked=0, isaddr=0
	sthx	*_strncmp_sloc0_1_0
;_strncmp.c:37: last++;
; checking lic
; checking IS_ITEMP
; pset=0, pget=0
;     genPlus
; IS_AOP_HX = 0
;     loadRegFromAop (hx, DIR(_strncmp_sloc1_1_0), 0)
	ldhx	*_strncmp_sloc1_1_0
	aix	#1
;     storeRegToAop (hx, DIR(_strncmp_sloc1_1_0), 0), stacked=0, isaddr=0
	sthx	*_strncmp_sloc1_1_0
; Peephole 3	- shortened jmp to bra
	bra	00105$
00107$:
;_strncmp.c:40: return( *first - *last );
;     genPointerGet
;     loadRegFromAop (hx, DIR(_strncmp_sloc0_1_0), 0)
	ldhx	*_strncmp_sloc0_1_0
	lda	,x
;     storeRegToAop (a, REG(-,-,x,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
;     genCast
;     loadRegFromAop (a, REG(-,-,x,a), 0)
; transferRegReg(a,a)
;     storeRegToAop (a, DIR(_strncmp_sloc2_1_0), 0), stacked=0, isaddr=0
	sta	*(_strncmp_sloc2_1_0 + 1)
;     loadRegFromAop (a, REG(-,-,x,a), 0)
; transferRegReg(a,a)
	rola	
	clra	
	sbc	#0x00
;     storeRegToAop (a, DIR(_strncmp_sloc2_1_0), 1), stacked=0, isaddr=0
	sta	*_strncmp_sloc2_1_0
; forgot to free a
;     genPointerGet
;     loadRegFromAop (hx, DIR(_strncmp_sloc1_1_0), 0)
	ldhx	*_strncmp_sloc1_1_0
	lda	,x
;     storeRegToAop (a, REG(-,-,x,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
;     genCast
;     loadRegFromAop (a, REG(-,-,x,a), 0)
; transferRegReg(a,a)
;     storeRegToAop (a, DIR(_strncmp_sloc1_1_0), 0), stacked=0, isaddr=0
	sta	*(_strncmp_sloc1_1_0 + 1)
;     loadRegFromAop (a, REG(-,-,x,a), 0)
; transferRegReg(a,a)
	rola	
	clra	
	sbc	#0x00
;     storeRegToAop (a, DIR(_strncmp_sloc1_1_0), 1), stacked=0, isaddr=0
	sta	*_strncmp_sloc1_1_0
; forgot to free a
;     genMinus
;     loadRegFromAop (a, DIR(_strncmp_sloc2_1_0), 0)
	lda	*(_strncmp_sloc2_1_0 + 1)
	sub	*(_strncmp_sloc1_1_0 + 1)
;     storeRegToAop (a, DIR(_strncmp_sloc2_1_0), 0), stacked=0, isaddr=0
	sta	*(_strncmp_sloc2_1_0 + 1)
;     loadRegFromAop (a, DIR(_strncmp_sloc2_1_0), 1)
	lda	*_strncmp_sloc2_1_0
	sbc	*_strncmp_sloc1_1_0
;     storeRegToAop (a, DIR(_strncmp_sloc2_1_0), 1), stacked=0, isaddr=0
	sta	*_strncmp_sloc2_1_0
;     genRet
;     loadRegFromAop (x, DIR(_strncmp_sloc2_1_0), 1)
	ldx	*_strncmp_sloc2_1_0
;     storeRegToAop (x, REG(-,-,-,x), 0), stacked=0, isaddr=0
; transferRegReg(x,x)
;     loadRegFromAop (a, DIR(_strncmp_sloc2_1_0), 0)
	lda	*(_strncmp_sloc2_1_0 + 1)
;     storeRegToAop (a, REG(-,-,-,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
00108$:
	rts
	.area CSEG (CODE)
	.area CONST   (CODE)
	.area XINIT
