;--------------------------------------------------------
; File Created by SDCC : FreeWare ANSI-C Compiler
; Version 2.6.1 #4330 (Oct 18 2006)
; This file generated Wed Oct 18 23:31:20 2006
;--------------------------------------------------------
	.module _strspn
	.optsdcc -mhc08
	
	.area HOME (CODE)
	.area GSINIT0 (CODE)
	.area GSINIT (CODE)
	.area GSFINAL (CODE)
	.area CSEG (CODE)
	.area XINIT
	.area CONST   (CODE)
	.area DSEG
	.area OSEG    (OVR)
	.area BSEG
	.area XSEG
	.area XISEG
;--------------------------------------------------------
; Public variables in this module
;--------------------------------------------------------
	.globl _strspn_PARM_2
	.globl _strspn
;--------------------------------------------------------
;  ram data
;--------------------------------------------------------
	.area DSEG
_strspn_count_1_1:
	.ds 2
_strspn_ch_1_1:
	.ds 1
_strspn_sloc0_1_0:
	.ds 2
_strspn_sloc1_1_0:
	.ds 1
;--------------------------------------------------------
; overlayable items in  ram 
;--------------------------------------------------------
	.area OSEG    (OVR)
;--------------------------------------------------------
; external initialized ram data
;--------------------------------------------------------
	.area XISEG
;--------------------------------------------------------
; extended address mode data
;--------------------------------------------------------
	.area XSEG
_strspn_PARM_2:
	.ds 2
_strspn_string_1_1:
	.ds 2
;--------------------------------------------------------
; global & static initialisations
;--------------------------------------------------------
	.area HOME (CODE)
	.area GSINIT (CODE)
	.area GSFINAL (CODE)
	.area GSINIT (CODE)
;--------------------------------------------------------
; Home
;--------------------------------------------------------
	.area HOME (CODE)
	.area CSEG (CODE)
;--------------------------------------------------------
; code
;--------------------------------------------------------
	.area CSEG (CODE)
;------------------------------------------------------------
;Allocation info for local variables in function 'strspn'
;------------------------------------------------------------
;count                     Allocated with name '_strspn_count_1_1'
;ch                        Allocated with name '_strspn_ch_1_1'
;sloc0                     Allocated with name '_strspn_sloc0_1_0'
;sloc1                     Allocated with name '_strspn_sloc1_1_0'
;control                   Allocated with name '_strspn_PARM_2'
;string                    Allocated with name '_strspn_string_1_1'
;------------------------------------------------------------
;_strspn.c:26: int strspn (
;	-----------------------------------------
;	 function strspn
;	-----------------------------------------
_strspn:
;     genReceive
;     loadRegFromAop (a, REG(-,-,-,a), 0)
; transferRegReg(a,a)
;     storeRegToAop (a, EXT(_strspn_string_1_1), 0), stacked=0, isaddr=0
	sta	(_strspn_string_1_1 + 1)
;     loadRegFromAop (x, REG(-,-,-,x), 0)
; transferRegReg(x,x)
;     storeRegToAop (x, EXT(_strspn_string_1_1), 1), stacked=0, isaddr=0
	stx	_strspn_string_1_1
;_strspn.c:34: while (ch = *string) {
;     genAssign
	clr	*_strspn_count_1_1
	clr	*(_strspn_count_1_1 + 1)
;     genAssign
;     loadRegFromAop (a, EXT(_strspn_string_1_1), 1)
	lda	_strspn_string_1_1
;     storeRegToAop (a, DIR(_strspn_sloc0_1_0), 1), stacked=0, isaddr=0
	sta	*_strspn_sloc0_1_0
;     loadRegFromAop (a, EXT(_strspn_string_1_1), 0)
	lda	(_strspn_string_1_1 + 1)
;     storeRegToAop (a, DIR(_strspn_sloc0_1_0), 0), stacked=0, isaddr=0
	sta	*(_strspn_sloc0_1_0 + 1)
00104$:
;     genPointerGet
;     loadRegFromAop (hx, DIR(_strspn_sloc0_1_0), 0)
	ldhx	*_strspn_sloc0_1_0
	lda	,x
;     storeRegToAop (a, DIR(_strspn_ch_1_1), 0), stacked=0, isaddr=0
	sta	*_strspn_ch_1_1
;     genAssign
	mov	*_strspn_ch_1_1,*_strspn_sloc1_1_0
;     genIfx
	tst	*_strspn_ch_1_1
;     genIfxJump
; Peephole 2d	- eliminated jmp
	beq	00106$
00113$:
;_strspn.c:35: if ( strchr(control,ch) )
;     genAssign
;     loadRegFromAop (a, DIR(_strspn_sloc1_1_0), 0)
	lda	*_strspn_sloc1_1_0
;     storeRegToAop (a, EXT(_strchr_PARM_2), 0), stacked=0, isaddr=1
	sta	_strchr_PARM_2
;     genCall
;     loadRegFromAop (x, EXT(_strspn_PARM_2), 1)
	ldx	_strspn_PARM_2
;     storeRegToAop (x, REG(-,-,-,x), 0), stacked=0, isaddr=0
; transferRegReg(x,x)
;     loadRegFromAop (a, EXT(_strspn_PARM_2), 0)
	lda	(_strspn_PARM_2 + 1)
;     storeRegToAop (a, REG(-,-,-,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
	jsr	_strchr
;     loadRegFromAop (a, REG(-,-,-,a), 0)
; transferRegReg(a,a)
;     storeRegToAop (a, REG(-,-,x,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
;     loadRegFromAop (x, REG(-,-,-,x), 0)
; transferRegReg(x,x)
;     storeRegToAop (x, REG(-,-,x,a), 1), stacked=0, isaddr=0
; transferRegReg(x,x)
;     genIfx
	tsta
	bne	00114$
	tstx
00114$:
;     genIfxJump
; Peephole 2d	- eliminated jmp
	beq	00106$
00115$:
; forgot to free a
;_strspn.c:36: count++ ;
; checking lic
; checking IS_ITEMP
; pset=0, pget=0
;     genPlus
; IS_AOP_HX = 0
;     loadRegFromAop (hx, DIR(_strspn_count_1_1), 0)
	ldhx	*_strspn_count_1_1
	aix	#1
;     storeRegToAop (hx, DIR(_strspn_count_1_1), 0), stacked=0, isaddr=0
	sthx	*_strspn_count_1_1
;_strspn.c:39: string++ ;
; checking lic
; checking IS_ITEMP
; pset=0, pget=0
;     genPlus
; IS_AOP_HX = 0
;     loadRegFromAop (hx, DIR(_strspn_sloc0_1_0), 0)
	ldhx	*_strspn_sloc0_1_0
	aix	#1
;     storeRegToAop (hx, DIR(_strspn_sloc0_1_0), 0), stacked=0, isaddr=0
	sthx	*_strspn_sloc0_1_0
; Peephole 3	- shortened jmp to bra
	bra	00104$
00106$:
;_strspn.c:42: return count ;
;     genRet
;     loadRegFromAop (x, DIR(_strspn_count_1_1), 1)
	ldx	*_strspn_count_1_1
;     storeRegToAop (x, REG(-,-,-,x), 0), stacked=0, isaddr=0
; transferRegReg(x,x)
;     loadRegFromAop (a, DIR(_strspn_count_1_1), 0)
	lda	*(_strspn_count_1_1 + 1)
;     storeRegToAop (a, REG(-,-,-,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
00107$:
	rts
	.area CSEG (CODE)
	.area CONST   (CODE)
	.area XINIT
