;--------------------------------------------------------
; File Created by SDCC : FreeWare ANSI-C Compiler
; Version 2.6.1 #4330 (Oct 18 2006)
; This file generated Wed Oct 18 23:31:08 2006
;--------------------------------------------------------
	.module _divslong
	.optsdcc -mhc08
	
	.area HOME (CODE)
	.area GSINIT0 (CODE)
	.area GSINIT (CODE)
	.area GSFINAL (CODE)
	.area CSEG (CODE)
	.area XINIT
	.area CONST   (CODE)
	.area DSEG
	.area OSEG    (OVR)
	.area BSEG
	.area XSEG
	.area XISEG
;--------------------------------------------------------
; Public variables in this module
;--------------------------------------------------------
	.globl __divslong_PARM_2
	.globl __divslong_PARM_1
	.globl __divslong
;--------------------------------------------------------
;  ram data
;--------------------------------------------------------
	.area DSEG
__divslong_sloc0_1_0:
	.ds 4
__divslong_sloc1_1_0:
	.ds 4
;--------------------------------------------------------
; overlayable items in  ram 
;--------------------------------------------------------
	.area OSEG    (OVR)
;--------------------------------------------------------
; external initialized ram data
;--------------------------------------------------------
	.area XISEG
;--------------------------------------------------------
; extended address mode data
;--------------------------------------------------------
	.area XSEG
__divslong_PARM_1:
	.ds 4
__divslong_PARM_2:
	.ds 4
__divslong_r_1_1:
	.ds 4
;--------------------------------------------------------
; global & static initialisations
;--------------------------------------------------------
	.area HOME (CODE)
	.area GSINIT (CODE)
	.area GSFINAL (CODE)
	.area GSINIT (CODE)
;--------------------------------------------------------
; Home
;--------------------------------------------------------
	.area HOME (CODE)
	.area CSEG (CODE)
;--------------------------------------------------------
; code
;--------------------------------------------------------
	.area CSEG (CODE)
;------------------------------------------------------------
;Allocation info for local variables in function '_divslong'
;------------------------------------------------------------
;sloc0                     Allocated with name '__divslong_sloc0_1_0'
;sloc1                     Allocated with name '__divslong_sloc1_1_0'
;x                         Allocated with name '__divslong_PARM_1'
;y                         Allocated with name '__divslong_PARM_2'
;r                         Allocated with name '__divslong_r_1_1'
;------------------------------------------------------------
;_divslong.c:255: _divslong (long x, long y)
;	-----------------------------------------
;	 function _divslong
;	-----------------------------------------
__divslong:
;_divslong.c:259: r = _divulong((x < 0 ? -x : x),
;     genCmp	(<)
;     loadRegFromAop (a, EXT(__divslong_PARM_1), 3)
	lda	__divslong_PARM_1
	sub	#0x00
; Peephole 2l	- eliminated bra
	bge	00106$
00113$:
;     genUminus
	clra
	sub	(__divslong_PARM_1 + 3)
;     storeRegToAop (a, DIR(__divslong_sloc0_1_0), 0), stacked=0, isaddr=0
	sta	*(__divslong_sloc0_1_0 + 3)
	clra
	sbc	(__divslong_PARM_1 + 2)
;     storeRegToAop (a, DIR(__divslong_sloc0_1_0), 1), stacked=0, isaddr=0
	sta	*(__divslong_sloc0_1_0 + 2)
	clra
	sbc	(__divslong_PARM_1 + 1)
;     storeRegToAop (a, DIR(__divslong_sloc0_1_0), 2), stacked=0, isaddr=0
	sta	*(__divslong_sloc0_1_0 + 1)
	clra
	sbc	__divslong_PARM_1
;     storeRegToAop (a, DIR(__divslong_sloc0_1_0), 3), stacked=0, isaddr=0
	sta	*__divslong_sloc0_1_0
; Peephole 3	- shortened jmp to bra
	bra	00107$
00106$:
;     genAssign
;     loadRegFromAop (a, EXT(__divslong_PARM_1), 3)
	lda	__divslong_PARM_1
;     storeRegToAop (a, DIR(__divslong_sloc0_1_0), 3), stacked=0, isaddr=0
	sta	*__divslong_sloc0_1_0
;     loadRegFromAop (a, EXT(__divslong_PARM_1), 2)
	lda	(__divslong_PARM_1 + 1)
;     storeRegToAop (a, DIR(__divslong_sloc0_1_0), 2), stacked=0, isaddr=0
	sta	*(__divslong_sloc0_1_0 + 1)
;     loadRegFromAop (a, EXT(__divslong_PARM_1), 1)
	lda	(__divslong_PARM_1 + 2)
;     storeRegToAop (a, DIR(__divslong_sloc0_1_0), 1), stacked=0, isaddr=0
	sta	*(__divslong_sloc0_1_0 + 2)
;     loadRegFromAop (a, EXT(__divslong_PARM_1), 0)
	lda	(__divslong_PARM_1 + 3)
;     storeRegToAop (a, DIR(__divslong_sloc0_1_0), 0), stacked=0, isaddr=0
	sta	*(__divslong_sloc0_1_0 + 3)
00107$:
;     genAssign
;_divslong.c:260: (y < 0 ? -y : y));
;     genCmp	(<)
;     loadRegFromAop (a, EXT(__divslong_PARM_2), 3)
	lda	__divslong_PARM_2
	sub	#0x00
; Peephole 2l	- eliminated bra
	bge	00108$
00114$:
;     genUminus
	clra
	sub	(__divslong_PARM_2 + 3)
;     storeRegToAop (a, DIR(__divslong_sloc1_1_0), 0), stacked=0, isaddr=0
	sta	*(__divslong_sloc1_1_0 + 3)
	clra
	sbc	(__divslong_PARM_2 + 2)
;     storeRegToAop (a, DIR(__divslong_sloc1_1_0), 1), stacked=0, isaddr=0
	sta	*(__divslong_sloc1_1_0 + 2)
	clra
	sbc	(__divslong_PARM_2 + 1)
;     storeRegToAop (a, DIR(__divslong_sloc1_1_0), 2), stacked=0, isaddr=0
	sta	*(__divslong_sloc1_1_0 + 1)
	clra
	sbc	__divslong_PARM_2
;     storeRegToAop (a, DIR(__divslong_sloc1_1_0), 3), stacked=0, isaddr=0
	sta	*__divslong_sloc1_1_0
; Peephole 3	- shortened jmp to bra
	bra	00109$
00108$:
;     genAssign
;     loadRegFromAop (a, EXT(__divslong_PARM_2), 3)
	lda	__divslong_PARM_2
;     storeRegToAop (a, DIR(__divslong_sloc1_1_0), 3), stacked=0, isaddr=0
	sta	*__divslong_sloc1_1_0
;     loadRegFromAop (a, EXT(__divslong_PARM_2), 2)
	lda	(__divslong_PARM_2 + 1)
;     storeRegToAop (a, DIR(__divslong_sloc1_1_0), 2), stacked=0, isaddr=0
	sta	*(__divslong_sloc1_1_0 + 1)
;     loadRegFromAop (a, EXT(__divslong_PARM_2), 1)
	lda	(__divslong_PARM_2 + 2)
;     storeRegToAop (a, DIR(__divslong_sloc1_1_0), 1), stacked=0, isaddr=0
	sta	*(__divslong_sloc1_1_0 + 2)
;     loadRegFromAop (a, EXT(__divslong_PARM_2), 0)
	lda	(__divslong_PARM_2 + 3)
;     storeRegToAop (a, DIR(__divslong_sloc1_1_0), 0), stacked=0, isaddr=0
	sta	*(__divslong_sloc1_1_0 + 3)
00109$:
;     genAssign
;     loadRegFromAop (a, DIR(__divslong_sloc0_1_0), 3)
	lda	*__divslong_sloc0_1_0
;     storeRegToAop (a, EXT(__divulong_PARM_1), 3), stacked=0, isaddr=1
	sta	__divulong_PARM_1
;     loadRegFromAop (a, DIR(__divslong_sloc0_1_0), 2)
	lda	*(__divslong_sloc0_1_0 + 1)
;     storeRegToAop (a, EXT(__divulong_PARM_1), 2), stacked=0, isaddr=1
	sta	(__divulong_PARM_1 + 1)
;     loadRegFromAop (a, DIR(__divslong_sloc0_1_0), 1)
	lda	*(__divslong_sloc0_1_0 + 2)
;     storeRegToAop (a, EXT(__divulong_PARM_1), 1), stacked=0, isaddr=1
	sta	(__divulong_PARM_1 + 2)
;     loadRegFromAop (a, DIR(__divslong_sloc0_1_0), 0)
	lda	*(__divslong_sloc0_1_0 + 3)
;     storeRegToAop (a, EXT(__divulong_PARM_1), 0), stacked=0, isaddr=1
	sta	(__divulong_PARM_1 + 3)
;     genAssign
;     loadRegFromAop (a, DIR(__divslong_sloc1_1_0), 3)
	lda	*__divslong_sloc1_1_0
;     storeRegToAop (a, EXT(__divulong_PARM_2), 3), stacked=0, isaddr=1
	sta	__divulong_PARM_2
;     loadRegFromAop (a, DIR(__divslong_sloc1_1_0), 2)
	lda	*(__divslong_sloc1_1_0 + 1)
;     storeRegToAop (a, EXT(__divulong_PARM_2), 2), stacked=0, isaddr=1
	sta	(__divulong_PARM_2 + 1)
;     loadRegFromAop (a, DIR(__divslong_sloc1_1_0), 1)
	lda	*(__divslong_sloc1_1_0 + 2)
;     storeRegToAop (a, EXT(__divulong_PARM_2), 1), stacked=0, isaddr=1
	sta	(__divulong_PARM_2 + 2)
;     loadRegFromAop (a, DIR(__divslong_sloc1_1_0), 0)
	lda	*(__divslong_sloc1_1_0 + 3)
;     storeRegToAop (a, EXT(__divulong_PARM_2), 0), stacked=0, isaddr=1
	sta	(__divulong_PARM_2 + 3)
;     genCall
	jsr	__divulong
;     loadRegFromAop (a, REG(-,-,-,a), 0)
; transferRegReg(a,a)
;     storeRegToAop (a, EXT(__divslong_r_1_1), 0), stacked=0, isaddr=0
	sta	(__divslong_r_1_1 + 3)
;     loadRegFromAop (x, REG(-,-,-,x), 0)
; transferRegReg(x,x)
;     storeRegToAop (x, EXT(__divslong_r_1_1), 1), stacked=0, isaddr=0
	stx	(__divslong_r_1_1 + 2)
;     loadRegFromAop (a, DIR(__ret2), 0)
	lda	*__ret2
;     storeRegToAop (a, EXT(__divslong_r_1_1), 2), stacked=0, isaddr=0
	sta	(__divslong_r_1_1 + 1)
;     loadRegFromAop (a, DIR(__ret3), 0)
	lda	*__ret3
;     storeRegToAop (a, EXT(__divslong_r_1_1), 3), stacked=0, isaddr=0
	sta	__divslong_r_1_1
;_divslong.c:261: if ( (x < 0) ^ (y < 0))
;     genCmp	(<)
;     loadRegFromAop (a, EXT(__divslong_PARM_1), 3)
	lda	__divslong_PARM_1
	sub	#0x00
	blt	00115$
	clra
	bra	00116$
00115$:
	lda	#0x01
00116$:
;     storeRegToAop (a, DIR(__divslong_sloc1_1_0), 0), stacked=0, isaddr=0
	sta	*__divslong_sloc1_1_0
; forgot to free a
; forgot to free xa
;     genCmp	(<)
;     loadRegFromAop (a, EXT(__divslong_PARM_2), 3)
	lda	__divslong_PARM_2
	sub	#0x00
	blt	00117$
	clra
	bra	00118$
00117$:
	lda	#0x01
00118$:
;     storeRegToAop (a, REG(-,-,x,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
; forgot to free a
; forgot to free xa
;     genXor
;     loadRegFromAop (a, REG(-,-,x,a), 0)
; transferRegReg(a,a)
	eor	*__divslong_sloc1_1_0
;     storeRegToAop (a, REG(-,-,x,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
;     genIfx
	tsta
;     genIfxJump
; Peephole 2d	- eliminated jmp
	beq	00102$
00119$:
; forgot to free a
;_divslong.c:262: return -r;
;     genUminus
	clra
	sub	(__divslong_r_1_1 + 3)
;     storeRegToAop (a, DIR(__divslong_sloc1_1_0), 0), stacked=0, isaddr=0
	sta	*(__divslong_sloc1_1_0 + 3)
	clra
	sbc	(__divslong_r_1_1 + 2)
;     storeRegToAop (a, DIR(__divslong_sloc1_1_0), 1), stacked=0, isaddr=0
	sta	*(__divslong_sloc1_1_0 + 2)
	clra
	sbc	(__divslong_r_1_1 + 1)
;     storeRegToAop (a, DIR(__divslong_sloc1_1_0), 2), stacked=0, isaddr=0
	sta	*(__divslong_sloc1_1_0 + 1)
	clra
	sbc	__divslong_r_1_1
;     storeRegToAop (a, DIR(__divslong_sloc1_1_0), 3), stacked=0, isaddr=0
	sta	*__divslong_sloc1_1_0
;     genRet
	mov	*__divslong_sloc1_1_0,*__ret3
	mov	*(__divslong_sloc1_1_0 + 1),*__ret2
;     loadRegFromAop (x, DIR(__divslong_sloc1_1_0), 1)
	ldx	*(__divslong_sloc1_1_0 + 2)
;     storeRegToAop (x, REG(-,-,-,x), 0), stacked=0, isaddr=0
; transferRegReg(x,x)
;     loadRegFromAop (a, DIR(__divslong_sloc1_1_0), 0)
	lda	*(__divslong_sloc1_1_0 + 3)
;     storeRegToAop (a, REG(-,-,-,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
; Peephole 3	- shortened jmp to bra
; Peephole 6b  - replaced jmp to rts with rts
	rts
00102$:
;_divslong.c:264: return r;
;     genRet
;     loadRegFromAop (a, EXT(__divslong_r_1_1), 3)
	lda	__divslong_r_1_1
;     storeRegToAop (a, DIR(__ret3), 0), stacked=0, isaddr=0
	sta	*__ret3
;     loadRegFromAop (a, EXT(__divslong_r_1_1), 2)
	lda	(__divslong_r_1_1 + 1)
;     storeRegToAop (a, DIR(__ret2), 0), stacked=0, isaddr=0
	sta	*__ret2
;     loadRegFromAop (x, EXT(__divslong_r_1_1), 1)
	ldx	(__divslong_r_1_1 + 2)
;     storeRegToAop (x, REG(-,-,-,x), 0), stacked=0, isaddr=0
; transferRegReg(x,x)
;     loadRegFromAop (a, EXT(__divslong_r_1_1), 0)
	lda	(__divslong_r_1_1 + 3)
;     storeRegToAop (a, REG(-,-,-,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
00104$:
	rts
	.area CSEG (CODE)
	.area CONST   (CODE)
	.area XINIT
