;--------------------------------------------------------
; File Created by SDCC : FreeWare ANSI-C Compiler
; Version 2.6.1 #4330 (Oct 18 2006)
; This file generated Wed Oct 18 23:31:08 2006
;--------------------------------------------------------
	.module _modslong
	.optsdcc -mhc08
	
	.area HOME (CODE)
	.area GSINIT0 (CODE)
	.area GSINIT (CODE)
	.area GSFINAL (CODE)
	.area CSEG (CODE)
	.area XINIT
	.area CONST   (CODE)
	.area DSEG
	.area OSEG    (OVR)
	.area BSEG
	.area XSEG
	.area XISEG
;--------------------------------------------------------
; Public variables in this module
;--------------------------------------------------------
	.globl __modslong_PARM_2
	.globl __modslong_PARM_1
	.globl __modslong
;--------------------------------------------------------
;  ram data
;--------------------------------------------------------
	.area DSEG
__modslong_sloc0_1_0:
	.ds 4
__modslong_sloc1_1_0:
	.ds 4
;--------------------------------------------------------
; overlayable items in  ram 
;--------------------------------------------------------
	.area OSEG    (OVR)
;--------------------------------------------------------
; external initialized ram data
;--------------------------------------------------------
	.area XISEG
;--------------------------------------------------------
; extended address mode data
;--------------------------------------------------------
	.area XSEG
__modslong_PARM_1:
	.ds 4
__modslong_PARM_2:
	.ds 4
__modslong_r_1_1:
	.ds 4
;--------------------------------------------------------
; global & static initialisations
;--------------------------------------------------------
	.area HOME (CODE)
	.area GSINIT (CODE)
	.area GSFINAL (CODE)
	.area GSINIT (CODE)
;--------------------------------------------------------
; Home
;--------------------------------------------------------
	.area HOME (CODE)
	.area CSEG (CODE)
;--------------------------------------------------------
; code
;--------------------------------------------------------
	.area CSEG (CODE)
;------------------------------------------------------------
;Allocation info for local variables in function '_modslong'
;------------------------------------------------------------
;sloc0                     Allocated with name '__modslong_sloc0_1_0'
;sloc1                     Allocated with name '__modslong_sloc1_1_0'
;a                         Allocated with name '__modslong_PARM_1'
;b                         Allocated with name '__modslong_PARM_2'
;r                         Allocated with name '__modslong_r_1_1'
;------------------------------------------------------------
;_modslong.c:256: _modslong (long a, long b)
;	-----------------------------------------
;	 function _modslong
;	-----------------------------------------
__modslong:
;_modslong.c:260: r = _modulong((a < 0 ? -a : a),
;     genCmp	(<)
;     loadRegFromAop (a, EXT(__modslong_PARM_1), 3)
	lda	__modslong_PARM_1
	sub	#0x00
; Peephole 2l	- eliminated bra
	bge	00106$
00113$:
;     genUminus
	clra
	sub	(__modslong_PARM_1 + 3)
;     storeRegToAop (a, DIR(__modslong_sloc0_1_0), 0), stacked=0, isaddr=0
	sta	*(__modslong_sloc0_1_0 + 3)
	clra
	sbc	(__modslong_PARM_1 + 2)
;     storeRegToAop (a, DIR(__modslong_sloc0_1_0), 1), stacked=0, isaddr=0
	sta	*(__modslong_sloc0_1_0 + 2)
	clra
	sbc	(__modslong_PARM_1 + 1)
;     storeRegToAop (a, DIR(__modslong_sloc0_1_0), 2), stacked=0, isaddr=0
	sta	*(__modslong_sloc0_1_0 + 1)
	clra
	sbc	__modslong_PARM_1
;     storeRegToAop (a, DIR(__modslong_sloc0_1_0), 3), stacked=0, isaddr=0
	sta	*__modslong_sloc0_1_0
; Peephole 3	- shortened jmp to bra
	bra	00107$
00106$:
;     genAssign
;     loadRegFromAop (a, EXT(__modslong_PARM_1), 3)
	lda	__modslong_PARM_1
;     storeRegToAop (a, DIR(__modslong_sloc0_1_0), 3), stacked=0, isaddr=0
	sta	*__modslong_sloc0_1_0
;     loadRegFromAop (a, EXT(__modslong_PARM_1), 2)
	lda	(__modslong_PARM_1 + 1)
;     storeRegToAop (a, DIR(__modslong_sloc0_1_0), 2), stacked=0, isaddr=0
	sta	*(__modslong_sloc0_1_0 + 1)
;     loadRegFromAop (a, EXT(__modslong_PARM_1), 1)
	lda	(__modslong_PARM_1 + 2)
;     storeRegToAop (a, DIR(__modslong_sloc0_1_0), 1), stacked=0, isaddr=0
	sta	*(__modslong_sloc0_1_0 + 2)
;     loadRegFromAop (a, EXT(__modslong_PARM_1), 0)
	lda	(__modslong_PARM_1 + 3)
;     storeRegToAop (a, DIR(__modslong_sloc0_1_0), 0), stacked=0, isaddr=0
	sta	*(__modslong_sloc0_1_0 + 3)
00107$:
;     genAssign
;_modslong.c:261: (b < 0 ? -b : b));
;     genCmp	(<)
;     loadRegFromAop (a, EXT(__modslong_PARM_2), 3)
	lda	__modslong_PARM_2
	sub	#0x00
; Peephole 2l	- eliminated bra
	bge	00108$
00114$:
;     genUminus
	clra
	sub	(__modslong_PARM_2 + 3)
;     storeRegToAop (a, DIR(__modslong_sloc1_1_0), 0), stacked=0, isaddr=0
	sta	*(__modslong_sloc1_1_0 + 3)
	clra
	sbc	(__modslong_PARM_2 + 2)
;     storeRegToAop (a, DIR(__modslong_sloc1_1_0), 1), stacked=0, isaddr=0
	sta	*(__modslong_sloc1_1_0 + 2)
	clra
	sbc	(__modslong_PARM_2 + 1)
;     storeRegToAop (a, DIR(__modslong_sloc1_1_0), 2), stacked=0, isaddr=0
	sta	*(__modslong_sloc1_1_0 + 1)
	clra
	sbc	__modslong_PARM_2
;     storeRegToAop (a, DIR(__modslong_sloc1_1_0), 3), stacked=0, isaddr=0
	sta	*__modslong_sloc1_1_0
; Peephole 3	- shortened jmp to bra
	bra	00109$
00108$:
;     genAssign
;     loadRegFromAop (a, EXT(__modslong_PARM_2), 3)
	lda	__modslong_PARM_2
;     storeRegToAop (a, DIR(__modslong_sloc1_1_0), 3), stacked=0, isaddr=0
	sta	*__modslong_sloc1_1_0
;     loadRegFromAop (a, EXT(__modslong_PARM_2), 2)
	lda	(__modslong_PARM_2 + 1)
;     storeRegToAop (a, DIR(__modslong_sloc1_1_0), 2), stacked=0, isaddr=0
	sta	*(__modslong_sloc1_1_0 + 1)
;     loadRegFromAop (a, EXT(__modslong_PARM_2), 1)
	lda	(__modslong_PARM_2 + 2)
;     storeRegToAop (a, DIR(__modslong_sloc1_1_0), 1), stacked=0, isaddr=0
	sta	*(__modslong_sloc1_1_0 + 2)
;     loadRegFromAop (a, EXT(__modslong_PARM_2), 0)
	lda	(__modslong_PARM_2 + 3)
;     storeRegToAop (a, DIR(__modslong_sloc1_1_0), 0), stacked=0, isaddr=0
	sta	*(__modslong_sloc1_1_0 + 3)
00109$:
;     genAssign
;     loadRegFromAop (a, DIR(__modslong_sloc0_1_0), 3)
	lda	*__modslong_sloc0_1_0
;     storeRegToAop (a, EXT(__modulong_PARM_1), 3), stacked=0, isaddr=1
	sta	__modulong_PARM_1
;     loadRegFromAop (a, DIR(__modslong_sloc0_1_0), 2)
	lda	*(__modslong_sloc0_1_0 + 1)
;     storeRegToAop (a, EXT(__modulong_PARM_1), 2), stacked=0, isaddr=1
	sta	(__modulong_PARM_1 + 1)
;     loadRegFromAop (a, DIR(__modslong_sloc0_1_0), 1)
	lda	*(__modslong_sloc0_1_0 + 2)
;     storeRegToAop (a, EXT(__modulong_PARM_1), 1), stacked=0, isaddr=1
	sta	(__modulong_PARM_1 + 2)
;     loadRegFromAop (a, DIR(__modslong_sloc0_1_0), 0)
	lda	*(__modslong_sloc0_1_0 + 3)
;     storeRegToAop (a, EXT(__modulong_PARM_1), 0), stacked=0, isaddr=1
	sta	(__modulong_PARM_1 + 3)
;     genAssign
;     loadRegFromAop (a, DIR(__modslong_sloc1_1_0), 3)
	lda	*__modslong_sloc1_1_0
;     storeRegToAop (a, EXT(__modulong_PARM_2), 3), stacked=0, isaddr=1
	sta	__modulong_PARM_2
;     loadRegFromAop (a, DIR(__modslong_sloc1_1_0), 2)
	lda	*(__modslong_sloc1_1_0 + 1)
;     storeRegToAop (a, EXT(__modulong_PARM_2), 2), stacked=0, isaddr=1
	sta	(__modulong_PARM_2 + 1)
;     loadRegFromAop (a, DIR(__modslong_sloc1_1_0), 1)
	lda	*(__modslong_sloc1_1_0 + 2)
;     storeRegToAop (a, EXT(__modulong_PARM_2), 1), stacked=0, isaddr=1
	sta	(__modulong_PARM_2 + 2)
;     loadRegFromAop (a, DIR(__modslong_sloc1_1_0), 0)
	lda	*(__modslong_sloc1_1_0 + 3)
;     storeRegToAop (a, EXT(__modulong_PARM_2), 0), stacked=0, isaddr=1
	sta	(__modulong_PARM_2 + 3)
;     genCall
	jsr	__modulong
;     loadRegFromAop (a, REG(-,-,-,a), 0)
; transferRegReg(a,a)
;     storeRegToAop (a, EXT(__modslong_r_1_1), 0), stacked=0, isaddr=0
	sta	(__modslong_r_1_1 + 3)
;     loadRegFromAop (x, REG(-,-,-,x), 0)
; transferRegReg(x,x)
;     storeRegToAop (x, EXT(__modslong_r_1_1), 1), stacked=0, isaddr=0
	stx	(__modslong_r_1_1 + 2)
;     loadRegFromAop (a, DIR(__ret2), 0)
	lda	*__ret2
;     storeRegToAop (a, EXT(__modslong_r_1_1), 2), stacked=0, isaddr=0
	sta	(__modslong_r_1_1 + 1)
;     loadRegFromAop (a, DIR(__ret3), 0)
	lda	*__ret3
;     storeRegToAop (a, EXT(__modslong_r_1_1), 3), stacked=0, isaddr=0
	sta	__modslong_r_1_1
;_modslong.c:262: if (a < 0)
;     genCmp	(<)
;     loadRegFromAop (a, EXT(__modslong_PARM_1), 3)
	lda	__modslong_PARM_1
	sub	#0x00
; Peephole 2l	- eliminated bra
	bge	00102$
00115$:
;_modslong.c:263: return -r;
;     genUminus
	clra
	sub	(__modslong_r_1_1 + 3)
;     storeRegToAop (a, DIR(__modslong_sloc1_1_0), 0), stacked=0, isaddr=0
	sta	*(__modslong_sloc1_1_0 + 3)
	clra
	sbc	(__modslong_r_1_1 + 2)
;     storeRegToAop (a, DIR(__modslong_sloc1_1_0), 1), stacked=0, isaddr=0
	sta	*(__modslong_sloc1_1_0 + 2)
	clra
	sbc	(__modslong_r_1_1 + 1)
;     storeRegToAop (a, DIR(__modslong_sloc1_1_0), 2), stacked=0, isaddr=0
	sta	*(__modslong_sloc1_1_0 + 1)
	clra
	sbc	__modslong_r_1_1
;     storeRegToAop (a, DIR(__modslong_sloc1_1_0), 3), stacked=0, isaddr=0
	sta	*__modslong_sloc1_1_0
;     genRet
	mov	*__modslong_sloc1_1_0,*__ret3
	mov	*(__modslong_sloc1_1_0 + 1),*__ret2
;     loadRegFromAop (x, DIR(__modslong_sloc1_1_0), 1)
	ldx	*(__modslong_sloc1_1_0 + 2)
;     storeRegToAop (x, REG(-,-,-,x), 0), stacked=0, isaddr=0
; transferRegReg(x,x)
;     loadRegFromAop (a, DIR(__modslong_sloc1_1_0), 0)
	lda	*(__modslong_sloc1_1_0 + 3)
;     storeRegToAop (a, REG(-,-,-,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
; Peephole 3	- shortened jmp to bra
; Peephole 6b  - replaced jmp to rts with rts
	rts
00102$:
;_modslong.c:265: return r;
;     genRet
;     loadRegFromAop (a, EXT(__modslong_r_1_1), 3)
	lda	__modslong_r_1_1
;     storeRegToAop (a, DIR(__ret3), 0), stacked=0, isaddr=0
	sta	*__ret3
;     loadRegFromAop (a, EXT(__modslong_r_1_1), 2)
	lda	(__modslong_r_1_1 + 1)
;     storeRegToAop (a, DIR(__ret2), 0), stacked=0, isaddr=0
	sta	*__ret2
;     loadRegFromAop (x, EXT(__modslong_r_1_1), 1)
	ldx	(__modslong_r_1_1 + 2)
;     storeRegToAop (x, REG(-,-,-,x), 0), stacked=0, isaddr=0
; transferRegReg(x,x)
;     loadRegFromAop (a, EXT(__modslong_r_1_1), 0)
	lda	(__modslong_r_1_1 + 3)
;     storeRegToAop (a, REG(-,-,-,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
00104$:
	rts
	.area CSEG (CODE)
	.area CONST   (CODE)
	.area XINIT
