;--------------------------------------------------------
; File Created by SDCC : FreeWare ANSI-C Compiler
; Version 2.6.1 #4330 (Oct 18 2006)
; This file generated Wed Oct 18 23:31:08 2006
;--------------------------------------------------------
	.module _modsint
	.optsdcc -mhc08
	
	.area HOME (CODE)
	.area GSINIT0 (CODE)
	.area GSINIT (CODE)
	.area GSFINAL (CODE)
	.area CSEG (CODE)
	.area XINIT
	.area CONST   (CODE)
	.area DSEG
	.area OSEG    (OVR)
	.area BSEG
	.area XSEG
	.area XISEG
;--------------------------------------------------------
; Public variables in this module
;--------------------------------------------------------
	.globl __modsint_PARM_2
	.globl __modsint
;--------------------------------------------------------
;  ram data
;--------------------------------------------------------
	.area DSEG
__modsint_r_1_1:
	.ds 2
__modsint_sloc0_1_0:
	.ds 2
__modsint_sloc1_1_0:
	.ds 2
;--------------------------------------------------------
; overlayable items in  ram 
;--------------------------------------------------------
	.area OSEG    (OVR)
;--------------------------------------------------------
; external initialized ram data
;--------------------------------------------------------
	.area XISEG
;--------------------------------------------------------
; extended address mode data
;--------------------------------------------------------
	.area XSEG
__modsint_PARM_2:
	.ds 2
__modsint_a_1_1:
	.ds 2
;--------------------------------------------------------
; global & static initialisations
;--------------------------------------------------------
	.area HOME (CODE)
	.area GSINIT (CODE)
	.area GSFINAL (CODE)
	.area GSINIT (CODE)
;--------------------------------------------------------
; Home
;--------------------------------------------------------
	.area HOME (CODE)
	.area CSEG (CODE)
;--------------------------------------------------------
; code
;--------------------------------------------------------
	.area CSEG (CODE)
;------------------------------------------------------------
;Allocation info for local variables in function '_modsint'
;------------------------------------------------------------
;r                         Allocated with name '__modsint_r_1_1'
;sloc0                     Allocated with name '__modsint_sloc0_1_0'
;sloc1                     Allocated with name '__modsint_sloc1_1_0'
;b                         Allocated with name '__modsint_PARM_2'
;a                         Allocated with name '__modsint_a_1_1'
;------------------------------------------------------------
;_modsint.c:199: int _modsint (int a, int b)
;	-----------------------------------------
;	 function _modsint
;	-----------------------------------------
__modsint:
;     genReceive
;     loadRegFromAop (a, REG(-,-,-,a), 0)
; transferRegReg(a,a)
;     storeRegToAop (a, EXT(__modsint_a_1_1), 0), stacked=0, isaddr=0
	sta	(__modsint_a_1_1 + 1)
;     loadRegFromAop (x, REG(-,-,-,x), 0)
; transferRegReg(x,x)
;     storeRegToAop (x, EXT(__modsint_a_1_1), 1), stacked=0, isaddr=0
	stx	__modsint_a_1_1
;_modsint.c:203: r = _moduint((a < 0 ? -a : a),
;     genCmp	(<)
;     loadRegFromAop (a, EXT(__modsint_a_1_1), 1)
	lda	__modsint_a_1_1
	sub	#0x00
; Peephole 2l	- eliminated bra
	bge	00106$
00113$:
;     genUminus
	clra
	sub	(__modsint_a_1_1 + 1)
;     storeRegToAop (a, DIR(__modsint_sloc0_1_0), 0), stacked=0, isaddr=0
	sta	*(__modsint_sloc0_1_0 + 1)
	clra
	sbc	__modsint_a_1_1
;     storeRegToAop (a, DIR(__modsint_sloc0_1_0), 1), stacked=0, isaddr=0
	sta	*__modsint_sloc0_1_0
; Peephole 3	- shortened jmp to bra
	bra	00107$
00106$:
;     genAssign
;     loadRegFromAop (a, EXT(__modsint_a_1_1), 1)
	lda	__modsint_a_1_1
;     storeRegToAop (a, DIR(__modsint_sloc0_1_0), 1), stacked=0, isaddr=0
	sta	*__modsint_sloc0_1_0
;     loadRegFromAop (a, EXT(__modsint_a_1_1), 0)
	lda	(__modsint_a_1_1 + 1)
;     storeRegToAop (a, DIR(__modsint_sloc0_1_0), 0), stacked=0, isaddr=0
	sta	*(__modsint_sloc0_1_0 + 1)
00107$:
;     genAssign
;_modsint.c:204: (b < 0 ? -b : b));
;     genCmp	(<)
;     loadRegFromAop (a, EXT(__modsint_PARM_2), 1)
	lda	__modsint_PARM_2
	sub	#0x00
; Peephole 2l	- eliminated bra
	bge	00108$
00114$:
;     genUminus
	clra
	sub	(__modsint_PARM_2 + 1)
;     storeRegToAop (a, DIR(__modsint_sloc1_1_0), 0), stacked=0, isaddr=0
	sta	*(__modsint_sloc1_1_0 + 1)
	clra
	sbc	__modsint_PARM_2
;     storeRegToAop (a, DIR(__modsint_sloc1_1_0), 1), stacked=0, isaddr=0
	sta	*__modsint_sloc1_1_0
; Peephole 3	- shortened jmp to bra
	bra	00109$
00108$:
;     genAssign
;     loadRegFromAop (a, EXT(__modsint_PARM_2), 1)
	lda	__modsint_PARM_2
;     storeRegToAop (a, DIR(__modsint_sloc1_1_0), 1), stacked=0, isaddr=0
	sta	*__modsint_sloc1_1_0
;     loadRegFromAop (a, EXT(__modsint_PARM_2), 0)
	lda	(__modsint_PARM_2 + 1)
;     storeRegToAop (a, DIR(__modsint_sloc1_1_0), 0), stacked=0, isaddr=0
	sta	*(__modsint_sloc1_1_0 + 1)
00109$:
;     genAssign
;     loadRegFromAop (a, DIR(__modsint_sloc1_1_0), 1)
	lda	*__modsint_sloc1_1_0
;     storeRegToAop (a, EXT(__moduint_PARM_2), 1), stacked=0, isaddr=1
	sta	__moduint_PARM_2
;     loadRegFromAop (a, DIR(__modsint_sloc1_1_0), 0)
	lda	*(__modsint_sloc1_1_0 + 1)
;     storeRegToAop (a, EXT(__moduint_PARM_2), 0), stacked=0, isaddr=1
	sta	(__moduint_PARM_2 + 1)
;     genCall
;     loadRegFromAop (x, DIR(__modsint_sloc0_1_0), 1)
	ldx	*__modsint_sloc0_1_0
;     storeRegToAop (x, REG(-,-,-,x), 0), stacked=0, isaddr=0
; transferRegReg(x,x)
;     loadRegFromAop (a, DIR(__modsint_sloc0_1_0), 0)
	lda	*(__modsint_sloc0_1_0 + 1)
;     storeRegToAop (a, REG(-,-,-,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
	jsr	__moduint
;     loadRegFromAop (a, REG(-,-,-,a), 0)
; transferRegReg(a,a)
;     storeRegToAop (a, DIR(__modsint_r_1_1), 0), stacked=0, isaddr=0
	sta	*(__modsint_r_1_1 + 1)
;     loadRegFromAop (x, REG(-,-,-,x), 0)
; transferRegReg(x,x)
;     storeRegToAop (x, DIR(__modsint_r_1_1), 1), stacked=0, isaddr=0
	stx	*__modsint_r_1_1
;_modsint.c:206: if (a < 0)
;     genCmp	(<)
;     loadRegFromAop (a, EXT(__modsint_a_1_1), 1)
	lda	__modsint_a_1_1
	sub	#0x00
; Peephole 2l	- eliminated bra
	bge	00102$
00115$:
;_modsint.c:207: return -r;
;     genUminus
	clra
	sub	*(__modsint_r_1_1 + 1)
;     storeRegToAop (a, DIR(__modsint_sloc1_1_0), 0), stacked=0, isaddr=0
	sta	*(__modsint_sloc1_1_0 + 1)
	clra
	sbc	*__modsint_r_1_1
;     storeRegToAop (a, DIR(__modsint_sloc1_1_0), 1), stacked=0, isaddr=0
	sta	*__modsint_sloc1_1_0
;     genRet
;     loadRegFromAop (x, DIR(__modsint_sloc1_1_0), 1)
	ldx	*__modsint_sloc1_1_0
;     storeRegToAop (x, REG(-,-,-,x), 0), stacked=0, isaddr=0
; transferRegReg(x,x)
;     loadRegFromAop (a, DIR(__modsint_sloc1_1_0), 0)
	lda	*(__modsint_sloc1_1_0 + 1)
;     storeRegToAop (a, REG(-,-,-,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
; Peephole 3	- shortened jmp to bra
; Peephole 6b  - replaced jmp to rts with rts
	rts
00102$:
;_modsint.c:209: return r;
;     genRet
;     loadRegFromAop (x, DIR(__modsint_r_1_1), 1)
	ldx	*__modsint_r_1_1
;     storeRegToAop (x, REG(-,-,-,x), 0), stacked=0, isaddr=0
; transferRegReg(x,x)
;     loadRegFromAop (a, DIR(__modsint_r_1_1), 0)
	lda	*(__modsint_r_1_1 + 1)
;     storeRegToAop (a, REG(-,-,-,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
00104$:
	rts
	.area CSEG (CODE)
	.area CONST   (CODE)
	.area XINIT
