;--------------------------------------------------------
; File Created by SDCC : FreeWare ANSI-C Compiler
; Version 2.6.1 #4330 (Oct 18 2006)
; This file generated Wed Oct 18 23:31:20 2006
;--------------------------------------------------------
	.module _strtok
	.optsdcc -mhc08
	
	.area HOME (CODE)
	.area GSINIT0 (CODE)
	.area GSINIT (CODE)
	.area GSFINAL (CODE)
	.area CSEG (CODE)
	.area XINIT
	.area CONST   (CODE)
	.area DSEG
	.area OSEG    (OVR)
	.area BSEG
	.area XSEG
	.area XISEG
;--------------------------------------------------------
; Public variables in this module
;--------------------------------------------------------
	.globl _strtok_PARM_2
	.globl _strtok
;--------------------------------------------------------
;  ram data
;--------------------------------------------------------
	.area DSEG
_strtok_sloc0_1_0:
	.ds 2
;--------------------------------------------------------
; overlayable items in  ram 
;--------------------------------------------------------
	.area OSEG    (OVR)
;--------------------------------------------------------
; external initialized ram data
;--------------------------------------------------------
	.area XISEG
;--------------------------------------------------------
; extended address mode data
;--------------------------------------------------------
	.area XSEG
_strtok_PARM_2:
	.ds 2
_strtok_str_1_1:
	.ds 2
_strtok_s_1_1:
	.ds 2
_strtok_s1_1_1:
	.ds 2
;--------------------------------------------------------
; global & static initialisations
;--------------------------------------------------------
	.area HOME (CODE)
	.area GSINIT (CODE)
	.area GSFINAL (CODE)
	.area GSINIT (CODE)
;--------------------------------------------------------
; Home
;--------------------------------------------------------
	.area HOME (CODE)
	.area CSEG (CODE)
;--------------------------------------------------------
; code
;--------------------------------------------------------
	.area CSEG (CODE)
;------------------------------------------------------------
;Allocation info for local variables in function 'strtok'
;------------------------------------------------------------
;sloc0                     Allocated with name '_strtok_sloc0_1_0'
;control                   Allocated with name '_strtok_PARM_2'
;str                       Allocated with name '_strtok_str_1_1'
;s                         Allocated with name '_strtok_s_1_1'
;s1                        Allocated with name '_strtok_s1_1_1'
;------------------------------------------------------------
;_strtok.c:31: char * strtok (
;	-----------------------------------------
;	 function strtok
;	-----------------------------------------
_strtok:
;     genReceive
;     loadRegFromAop (a, REG(-,-,-,a), 0)
; transferRegReg(a,a)
;     storeRegToAop (a, EXT(_strtok_str_1_1), 0), stacked=0, isaddr=0
	sta	(_strtok_str_1_1 + 1)
;     loadRegFromAop (x, REG(-,-,-,x), 0)
; transferRegReg(x,x)
;     storeRegToAop (x, EXT(_strtok_str_1_1), 1), stacked=0, isaddr=0
	stx	_strtok_str_1_1
;_strtok.c:38: if ( str )
;     genIfx
;     loadRegFromAop (a, EXT(_strtok_str_1_1), 0)
	lda	(_strtok_str_1_1 + 1)
	ora	_strtok_str_1_1
;     genIfxJump
; Peephole 2d	- eliminated jmp
	beq	00102$
00130$:
;_strtok.c:39: s = str ;
;     genAssign
;     loadRegFromAop (a, EXT(_strtok_str_1_1), 1)
	lda	_strtok_str_1_1
;     storeRegToAop (a, EXT(_strtok_s_1_1), 1), stacked=0, isaddr=1
	sta	_strtok_s_1_1
;     loadRegFromAop (a, EXT(_strtok_str_1_1), 0)
	lda	(_strtok_str_1_1 + 1)
;     storeRegToAop (a, EXT(_strtok_s_1_1), 0), stacked=0, isaddr=1
	sta	(_strtok_s_1_1 + 1)
00102$:
;_strtok.c:40: if ( !s )
;     genIfx
;     loadRegFromAop (a, EXT(_strtok_s_1_1), 0)
	lda	(_strtok_s_1_1 + 1)
	ora	_strtok_s_1_1
;     genIfxJump
; Peephole 2c	- eliminated jmp
	bne	00108$
00131$:
;_strtok.c:41: return NULL;
;     genRet
;     loadRegFromAop (x, LIT(#0x00), 1)
	clrx
;     storeRegToAop (x, REG(-,-,-,x), 0), stacked=0, isaddr=0
; transferRegReg(x,x)
;     loadRegFromAop (a, LIT(#0x00), 0)
	clra
;     storeRegToAop (a, REG(-,-,-,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
; Peephole 6a  - replaced jmp to rts with rts
	rts
;_strtok.c:43: while (*s) {
00108$:
;     genAssign
;     loadRegFromAop (a, EXT(_strtok_s_1_1), 1)
	lda	_strtok_s_1_1
;     storeRegToAop (a, DIR(_strtok_sloc0_1_0), 1), stacked=0, isaddr=0
	sta	*_strtok_sloc0_1_0
;     loadRegFromAop (a, EXT(_strtok_s_1_1), 0)
	lda	(_strtok_s_1_1 + 1)
;     storeRegToAop (a, DIR(_strtok_sloc0_1_0), 0), stacked=0, isaddr=0
	sta	*(_strtok_sloc0_1_0 + 1)
;     genPointerGet
;     loadRegFromAop (hx, DIR(_strtok_sloc0_1_0), 0)
	ldhx	*_strtok_sloc0_1_0
	lda	,x
;     genIfxJump
; Peephole 2d	- eliminated jmp
	beq	00110$
00132$:
;_strtok.c:44: if (strchr(control,*s))
;     genPointerGet
;     loadRegFromAop (hx, DIR(_strtok_sloc0_1_0), 0)
	ldhx	*_strtok_sloc0_1_0
	lda	,x
;     storeRegToAop (a, EXT(_strchr_PARM_2), 0), stacked=0, isaddr=1
	sta	_strchr_PARM_2
;     genCall
;     loadRegFromAop (x, EXT(_strtok_PARM_2), 1)
	ldx	_strtok_PARM_2
;     storeRegToAop (x, REG(-,-,-,x), 0), stacked=0, isaddr=0
; transferRegReg(x,x)
;     loadRegFromAop (a, EXT(_strtok_PARM_2), 0)
	lda	(_strtok_PARM_2 + 1)
;     storeRegToAop (a, REG(-,-,-,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
	jsr	_strchr
;     loadRegFromAop (a, REG(-,-,-,a), 0)
; transferRegReg(a,a)
;     storeRegToAop (a, REG(-,-,x,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
;     loadRegFromAop (x, REG(-,-,-,x), 0)
; transferRegReg(x,x)
;     storeRegToAop (x, REG(-,-,x,a), 1), stacked=0, isaddr=0
; transferRegReg(x,x)
;     genIfx
	tsta
	bne	00133$
	tstx
00133$:
;     genIfxJump
; Peephole 2d	- eliminated jmp
	beq	00110$
00134$:
; forgot to free a
;_strtok.c:45: s++;
; checking lic
; checking IS_ITEMP
;     genPlus
; IS_AOP_HX = 0
; icount = 1, sameRegs=1
;     genPlusIncr
;     loadRegFromAop (a, EXT(_strtok_s_1_1), 0)
	lda	(_strtok_s_1_1 + 1)
	inca
;     storeRegToAop (a, EXT(_strtok_s_1_1), 0), stacked=0, isaddr=1
	sta	(_strtok_s_1_1 + 1)
	bne	00135$
;     loadRegFromAop (a, EXT(_strtok_s_1_1), 1)
	lda	_strtok_s_1_1
	inca
;     storeRegToAop (a, EXT(_strtok_s_1_1), 1), stacked=0, isaddr=1
	sta	_strtok_s_1_1
00135$:
; Peephole 3	- shortened jmp to bra
	bra	00108$
;_strtok.c:47: break;
00110$:
;_strtok.c:50: s1 = s ;
;     genAssign
;     loadRegFromAop (a, EXT(_strtok_s_1_1), 1)
	lda	_strtok_s_1_1
;     storeRegToAop (a, EXT(_strtok_s1_1_1), 1), stacked=0, isaddr=0
	sta	_strtok_s1_1_1
;     loadRegFromAop (a, EXT(_strtok_s_1_1), 0)
	lda	(_strtok_s_1_1 + 1)
;     storeRegToAop (a, EXT(_strtok_s1_1_1), 0), stacked=0, isaddr=0
	sta	(_strtok_s1_1_1 + 1)
;_strtok.c:52: while (*s) {
00113$:
;     genAssign
;     loadRegFromAop (a, EXT(_strtok_s_1_1), 1)
	lda	_strtok_s_1_1
;     storeRegToAop (a, DIR(_strtok_sloc0_1_0), 1), stacked=0, isaddr=0
	sta	*_strtok_sloc0_1_0
;     loadRegFromAop (a, EXT(_strtok_s_1_1), 0)
	lda	(_strtok_s_1_1 + 1)
;     storeRegToAop (a, DIR(_strtok_sloc0_1_0), 0), stacked=0, isaddr=0
	sta	*(_strtok_sloc0_1_0 + 1)
;     genPointerGet
;     loadRegFromAop (hx, DIR(_strtok_sloc0_1_0), 0)
	ldhx	*_strtok_sloc0_1_0
	lda	,x
;     genIfxJump
; Peephole 2d	- eliminated jmp
	beq	00115$
00136$:
;_strtok.c:53: if (strchr(control,*s)) {
;     genPointerGet
;     loadRegFromAop (hx, DIR(_strtok_sloc0_1_0), 0)
	ldhx	*_strtok_sloc0_1_0
	lda	,x
;     storeRegToAop (a, EXT(_strchr_PARM_2), 0), stacked=0, isaddr=1
	sta	_strchr_PARM_2
;     genCall
;     loadRegFromAop (x, EXT(_strtok_PARM_2), 1)
	ldx	_strtok_PARM_2
;     storeRegToAop (x, REG(-,-,-,x), 0), stacked=0, isaddr=0
; transferRegReg(x,x)
;     loadRegFromAop (a, EXT(_strtok_PARM_2), 0)
	lda	(_strtok_PARM_2 + 1)
;     storeRegToAop (a, REG(-,-,-,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
	jsr	_strchr
;     loadRegFromAop (a, REG(-,-,-,a), 0)
; transferRegReg(a,a)
;     storeRegToAop (a, REG(-,-,x,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
;     loadRegFromAop (x, REG(-,-,-,x), 0)
; transferRegReg(x,x)
;     storeRegToAop (x, REG(-,-,x,a), 1), stacked=0, isaddr=0
; transferRegReg(x,x)
;     genIfx
	tsta
	bne	00137$
	tstx
00137$:
;     genIfxJump
; Peephole 2d	- eliminated jmp
	beq	00112$
00138$:
; forgot to free a
;_strtok.c:54: *s++ = '\0';
;     genAssign
;     loadRegFromAop (a, EXT(_strtok_s_1_1), 1)
	lda	_strtok_s_1_1
;     storeRegToAop (a, DIR(_strtok_sloc0_1_0), 1), stacked=0, isaddr=0
	sta	*_strtok_sloc0_1_0
;     loadRegFromAop (a, EXT(_strtok_s_1_1), 0)
	lda	(_strtok_s_1_1 + 1)
;     storeRegToAop (a, DIR(_strtok_sloc0_1_0), 0), stacked=0, isaddr=0
	sta	*(_strtok_sloc0_1_0 + 1)
;     genPointerSet
;     loadRegFromAop (hx, DIR(_strtok_sloc0_1_0), 0)
	ldhx	*_strtok_sloc0_1_0
;     loadRegFromAop (a, LIT(#0x00), 0)
	clra
	sta	,x
; checking lic
; checking IS_ITEMP
;     genPlus
; IS_AOP_HX = 0
; icount = 1, sameRegs=0
;  left size = 2
;  right size = 1
;  result size = 2
;     loadRegFromAop (a, DIR(_strtok_sloc0_1_0), 0)
	lda	*(_strtok_sloc0_1_0 + 1)
	add	#0x01
;     storeRegToAop (a, EXT(_strtok_s_1_1), 0), stacked=0, isaddr=1
	sta	(_strtok_s_1_1 + 1)
;     loadRegFromAop (a, DIR(_strtok_sloc0_1_0), 1)
	lda	*_strtok_sloc0_1_0
	adc	#0x00
;     storeRegToAop (a, EXT(_strtok_s_1_1), 1), stacked=0, isaddr=1
	sta	_strtok_s_1_1
;_strtok.c:55: return s1 ;
;     genRet
;     loadRegFromAop (x, EXT(_strtok_s1_1_1), 1)
	ldx	_strtok_s1_1_1
;     storeRegToAop (x, REG(-,-,-,x), 0), stacked=0, isaddr=0
; transferRegReg(x,x)
;     loadRegFromAop (a, EXT(_strtok_s1_1_1), 0)
	lda	(_strtok_s1_1_1 + 1)
;     storeRegToAop (a, REG(-,-,-,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
; Peephole 3	- shortened jmp to bra
; Peephole 6b  - replaced jmp to rts with rts
	rts
00112$:
;_strtok.c:57: s++ ;
; checking lic
; checking IS_ITEMP
;     genPlus
; IS_AOP_HX = 0
; icount = 1, sameRegs=1
;     genPlusIncr
;     loadRegFromAop (a, EXT(_strtok_s_1_1), 0)
	lda	(_strtok_s_1_1 + 1)
	inca
;     storeRegToAop (a, EXT(_strtok_s_1_1), 0), stacked=0, isaddr=1
	sta	(_strtok_s_1_1 + 1)
	bne	00139$
;     loadRegFromAop (a, EXT(_strtok_s_1_1), 1)
	lda	_strtok_s_1_1
	inca
;     storeRegToAop (a, EXT(_strtok_s_1_1), 1), stacked=0, isaddr=1
	sta	_strtok_s_1_1
00139$:
; Peephole 3	- shortened jmp to bra
	bra	00113$
00115$:
;_strtok.c:60: s = NULL;
;     genAssign
;     loadRegFromAop (a, LIT(#0x00), 1)
;     storeRegToAop (a, EXT(_strtok_s_1_1), 1), stacked=0, isaddr=1
;     loadRegFromAop (a, LIT(#0x00), 0)
;     storeRegToAop (a, EXT(_strtok_s_1_1), 0), stacked=0, isaddr=1
; Peephole 5c   - eliminated redundant clra
	clra
	sta	_strtok_s_1_1
	sta	(_strtok_s_1_1 + 1)
;_strtok.c:62: if (*s1)
;     genPointerGet
;     loadRegFromAop (hx, EXT(_strtok_s1_1_1), 0)
;     loadRegFromAop (a, EXT(_strtok_s1_1_1), 1)
	lda	_strtok_s1_1_1
;     loadRegFromAop (x, EXT(_strtok_s1_1_1), 0)
	ldx	(_strtok_s1_1_1 + 1)
; transferRegReg(a,h)
	psha
	pulh
	lda	,x
;     genIfxJump
; Peephole 2d	- eliminated jmp
	beq	00117$
00140$:
;_strtok.c:63: return s1;
;     genRet
;     loadRegFromAop (x, EXT(_strtok_s1_1_1), 1)
	ldx	_strtok_s1_1_1
;     storeRegToAop (x, REG(-,-,-,x), 0), stacked=0, isaddr=0
; transferRegReg(x,x)
;     loadRegFromAop (a, EXT(_strtok_s1_1_1), 0)
	lda	(_strtok_s1_1_1 + 1)
;     storeRegToAop (a, REG(-,-,-,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
; Peephole 3	- shortened jmp to bra
; Peephole 6b  - replaced jmp to rts with rts
	rts
00117$:
;_strtok.c:65: return NULL;
;     genRet
;     loadRegFromAop (x, LIT(#0x00), 1)
	clrx
;     storeRegToAop (x, REG(-,-,-,x), 0), stacked=0, isaddr=0
; transferRegReg(x,x)
;     loadRegFromAop (a, LIT(#0x00), 0)
	clra
;     storeRegToAop (a, REG(-,-,-,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
00119$:
	rts
	.area CSEG (CODE)
	.area CONST   (CODE)
	.area XINIT
