;--------------------------------------------------------
; File Created by SDCC : FreeWare ANSI-C Compiler
; Version 2.6.1 #4330 (Oct 18 2006)
; This file generated Wed Oct 18 23:31:08 2006
;--------------------------------------------------------
	.module _divsint
	.optsdcc -mhc08
	
	.area HOME (CODE)
	.area GSINIT0 (CODE)
	.area GSINIT (CODE)
	.area GSFINAL (CODE)
	.area CSEG (CODE)
	.area XINIT
	.area CONST   (CODE)
	.area DSEG
	.area OSEG    (OVR)
	.area BSEG
	.area XSEG
	.area XISEG
;--------------------------------------------------------
; Public variables in this module
;--------------------------------------------------------
	.globl __divsint_PARM_2
	.globl __divsint
;--------------------------------------------------------
;  ram data
;--------------------------------------------------------
	.area DSEG
__divsint_r_1_1:
	.ds 2
__divsint_sloc0_1_0:
	.ds 2
__divsint_sloc1_1_0:
	.ds 2
;--------------------------------------------------------
; overlayable items in  ram 
;--------------------------------------------------------
	.area OSEG    (OVR)
;--------------------------------------------------------
; external initialized ram data
;--------------------------------------------------------
	.area XISEG
;--------------------------------------------------------
; extended address mode data
;--------------------------------------------------------
	.area XSEG
__divsint_PARM_2:
	.ds 2
__divsint_x_1_1:
	.ds 2
;--------------------------------------------------------
; global & static initialisations
;--------------------------------------------------------
	.area HOME (CODE)
	.area GSINIT (CODE)
	.area GSFINAL (CODE)
	.area GSINIT (CODE)
;--------------------------------------------------------
; Home
;--------------------------------------------------------
	.area HOME (CODE)
	.area CSEG (CODE)
;--------------------------------------------------------
; code
;--------------------------------------------------------
	.area CSEG (CODE)
;------------------------------------------------------------
;Allocation info for local variables in function '_divsint'
;------------------------------------------------------------
;r                         Allocated with name '__divsint_r_1_1'
;sloc0                     Allocated with name '__divsint_sloc0_1_0'
;sloc1                     Allocated with name '__divsint_sloc1_1_0'
;y                         Allocated with name '__divsint_PARM_2'
;x                         Allocated with name '__divsint_x_1_1'
;------------------------------------------------------------
;_divsint.c:203: _divsint (int x, int y)
;	-----------------------------------------
;	 function _divsint
;	-----------------------------------------
__divsint:
;     genReceive
;     loadRegFromAop (a, REG(-,-,-,a), 0)
; transferRegReg(a,a)
;     storeRegToAop (a, EXT(__divsint_x_1_1), 0), stacked=0, isaddr=0
	sta	(__divsint_x_1_1 + 1)
;     loadRegFromAop (x, REG(-,-,-,x), 0)
; transferRegReg(x,x)
;     storeRegToAop (x, EXT(__divsint_x_1_1), 1), stacked=0, isaddr=0
	stx	__divsint_x_1_1
;_divsint.c:207: r = _divuint((x < 0 ? -x : x),
;     genCmp	(<)
;     loadRegFromAop (a, EXT(__divsint_x_1_1), 1)
	lda	__divsint_x_1_1
	sub	#0x00
; Peephole 2l	- eliminated bra
	bge	00106$
00113$:
;     genUminus
	clra
	sub	(__divsint_x_1_1 + 1)
;     storeRegToAop (a, DIR(__divsint_sloc0_1_0), 0), stacked=0, isaddr=0
	sta	*(__divsint_sloc0_1_0 + 1)
	clra
	sbc	__divsint_x_1_1
;     storeRegToAop (a, DIR(__divsint_sloc0_1_0), 1), stacked=0, isaddr=0
	sta	*__divsint_sloc0_1_0
; Peephole 3	- shortened jmp to bra
	bra	00107$
00106$:
;     genAssign
;     loadRegFromAop (a, EXT(__divsint_x_1_1), 1)
	lda	__divsint_x_1_1
;     storeRegToAop (a, DIR(__divsint_sloc0_1_0), 1), stacked=0, isaddr=0
	sta	*__divsint_sloc0_1_0
;     loadRegFromAop (a, EXT(__divsint_x_1_1), 0)
	lda	(__divsint_x_1_1 + 1)
;     storeRegToAop (a, DIR(__divsint_sloc0_1_0), 0), stacked=0, isaddr=0
	sta	*(__divsint_sloc0_1_0 + 1)
00107$:
;     genAssign
;_divsint.c:208: (y < 0 ? -y : y));
;     genCmp	(<)
;     loadRegFromAop (a, EXT(__divsint_PARM_2), 1)
	lda	__divsint_PARM_2
	sub	#0x00
; Peephole 2l	- eliminated bra
	bge	00108$
00114$:
;     genUminus
	clra
	sub	(__divsint_PARM_2 + 1)
;     storeRegToAop (a, DIR(__divsint_sloc1_1_0), 0), stacked=0, isaddr=0
	sta	*(__divsint_sloc1_1_0 + 1)
	clra
	sbc	__divsint_PARM_2
;     storeRegToAop (a, DIR(__divsint_sloc1_1_0), 1), stacked=0, isaddr=0
	sta	*__divsint_sloc1_1_0
; Peephole 3	- shortened jmp to bra
	bra	00109$
00108$:
;     genAssign
;     loadRegFromAop (a, EXT(__divsint_PARM_2), 1)
	lda	__divsint_PARM_2
;     storeRegToAop (a, DIR(__divsint_sloc1_1_0), 1), stacked=0, isaddr=0
	sta	*__divsint_sloc1_1_0
;     loadRegFromAop (a, EXT(__divsint_PARM_2), 0)
	lda	(__divsint_PARM_2 + 1)
;     storeRegToAop (a, DIR(__divsint_sloc1_1_0), 0), stacked=0, isaddr=0
	sta	*(__divsint_sloc1_1_0 + 1)
00109$:
;     genAssign
;     loadRegFromAop (a, DIR(__divsint_sloc1_1_0), 1)
	lda	*__divsint_sloc1_1_0
;     storeRegToAop (a, EXT(__divuint_PARM_2), 1), stacked=0, isaddr=1
	sta	__divuint_PARM_2
;     loadRegFromAop (a, DIR(__divsint_sloc1_1_0), 0)
	lda	*(__divsint_sloc1_1_0 + 1)
;     storeRegToAop (a, EXT(__divuint_PARM_2), 0), stacked=0, isaddr=1
	sta	(__divuint_PARM_2 + 1)
;     genCall
;     loadRegFromAop (x, DIR(__divsint_sloc0_1_0), 1)
	ldx	*__divsint_sloc0_1_0
;     storeRegToAop (x, REG(-,-,-,x), 0), stacked=0, isaddr=0
; transferRegReg(x,x)
;     loadRegFromAop (a, DIR(__divsint_sloc0_1_0), 0)
	lda	*(__divsint_sloc0_1_0 + 1)
;     storeRegToAop (a, REG(-,-,-,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
	jsr	__divuint
;     loadRegFromAop (a, REG(-,-,-,a), 0)
; transferRegReg(a,a)
;     storeRegToAop (a, DIR(__divsint_r_1_1), 0), stacked=0, isaddr=0
	sta	*(__divsint_r_1_1 + 1)
;     loadRegFromAop (x, REG(-,-,-,x), 0)
; transferRegReg(x,x)
;     storeRegToAop (x, DIR(__divsint_r_1_1), 1), stacked=0, isaddr=0
	stx	*__divsint_r_1_1
;_divsint.c:209: if ( (x < 0) ^ (y < 0))
;     genCmp	(<)
;     loadRegFromAop (a, EXT(__divsint_x_1_1), 1)
	lda	__divsint_x_1_1
	sub	#0x00
	blt	00115$
	clra
	bra	00116$
00115$:
	lda	#0x01
00116$:
;     storeRegToAop (a, DIR(__divsint_sloc1_1_0), 0), stacked=0, isaddr=0
	sta	*__divsint_sloc1_1_0
; forgot to free a
; forgot to free xa
;     genCmp	(<)
;     loadRegFromAop (a, EXT(__divsint_PARM_2), 1)
	lda	__divsint_PARM_2
	sub	#0x00
	blt	00117$
	clra
	bra	00118$
00117$:
	lda	#0x01
00118$:
;     storeRegToAop (a, REG(-,-,x,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
; forgot to free a
; forgot to free xa
;     genXor
;     loadRegFromAop (a, REG(-,-,x,a), 0)
; transferRegReg(a,a)
	eor	*__divsint_sloc1_1_0
;     storeRegToAop (a, REG(-,-,x,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
;     genIfx
	tsta
;     genIfxJump
; Peephole 2d	- eliminated jmp
	beq	00102$
00119$:
; forgot to free a
;_divsint.c:210: return -r;
;     genUminus
	clra
	sub	*(__divsint_r_1_1 + 1)
;     storeRegToAop (a, DIR(__divsint_sloc1_1_0), 0), stacked=0, isaddr=0
	sta	*(__divsint_sloc1_1_0 + 1)
	clra
	sbc	*__divsint_r_1_1
;     storeRegToAop (a, DIR(__divsint_sloc1_1_0), 1), stacked=0, isaddr=0
	sta	*__divsint_sloc1_1_0
;     genRet
;     loadRegFromAop (x, DIR(__divsint_sloc1_1_0), 1)
	ldx	*__divsint_sloc1_1_0
;     storeRegToAop (x, REG(-,-,-,x), 0), stacked=0, isaddr=0
; transferRegReg(x,x)
;     loadRegFromAop (a, DIR(__divsint_sloc1_1_0), 0)
	lda	*(__divsint_sloc1_1_0 + 1)
;     storeRegToAop (a, REG(-,-,-,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
; Peephole 3	- shortened jmp to bra
; Peephole 6b  - replaced jmp to rts with rts
	rts
00102$:
;_divsint.c:212: return r;
;     genRet
;     loadRegFromAop (x, DIR(__divsint_r_1_1), 1)
	ldx	*__divsint_r_1_1
;     storeRegToAop (x, REG(-,-,-,x), 0), stacked=0, isaddr=0
; transferRegReg(x,x)
;     loadRegFromAop (a, DIR(__divsint_r_1_1), 0)
	lda	*(__divsint_r_1_1 + 1)
;     storeRegToAop (a, REG(-,-,-,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
00104$:
	rts
	.area CSEG (CODE)
	.area CONST   (CODE)
	.area XINIT
