;--------------------------------------------------------
; File Created by SDCC : FreeWare ANSI-C Compiler
; Version 2.6.1 #4330 (Oct 18 2006)
; This file generated Wed Oct 18 23:31:28 2006
;--------------------------------------------------------
	.module asinf
	.optsdcc -mhc08
	
	.area HOME (CODE)
	.area GSINIT0 (CODE)
	.area GSINIT (CODE)
	.area GSFINAL (CODE)
	.area CSEG (CODE)
	.area XINIT
	.area CONST   (CODE)
	.area DSEG
	.area OSEG    (OVR)
	.area BSEG
	.area XSEG
	.area XISEG
;--------------------------------------------------------
; Public variables in this module
;--------------------------------------------------------
	.globl _asinf
;--------------------------------------------------------
;  ram data
;--------------------------------------------------------
	.area DSEG
;--------------------------------------------------------
; overlayable items in  ram 
;--------------------------------------------------------
	.area OSEG    (OVR)
;--------------------------------------------------------
; external initialized ram data
;--------------------------------------------------------
	.area XISEG
;--------------------------------------------------------
; extended address mode data
;--------------------------------------------------------
	.area XSEG
;--------------------------------------------------------
; global & static initialisations
;--------------------------------------------------------
	.area HOME (CODE)
	.area GSINIT (CODE)
	.area GSFINAL (CODE)
	.area GSINIT (CODE)
;--------------------------------------------------------
; Home
;--------------------------------------------------------
	.area HOME (CODE)
	.area CSEG (CODE)
;--------------------------------------------------------
; code
;--------------------------------------------------------
	.area CSEG (CODE)
;------------------------------------------------------------
;Allocation info for local variables in function 'asinf'
;------------------------------------------------------------
;x                         Allocated to stack - offset 2
;sloc0                     Allocated to stack - offset -4
;------------------------------------------------------------
;asinf.c:25: float asinf(const float x) _FLOAT_FUNC_REENTRANT
;	-----------------------------------------
;	 function asinf
;	-----------------------------------------
_asinf:
	ais	#-4
;asinf.c:27: if(x== 1.0) return  HALF_PI;
;     genAssign
;     loadRegFromAop (a, SOF(x), 3)
	lda	7,s
;     storeRegToAop (a, EXT(___fseq_PARM_1), 3), stacked=0, isaddr=1
	sta	___fseq_PARM_1
;     loadRegFromAop (a, SOF(x), 2)
	lda	8,s
;     storeRegToAop (a, EXT(___fseq_PARM_1), 2), stacked=0, isaddr=1
	sta	(___fseq_PARM_1 + 1)
;     loadRegFromAop (a, SOF(x), 1)
	lda	9,s
;     storeRegToAop (a, EXT(___fseq_PARM_1), 1), stacked=0, isaddr=1
	sta	(___fseq_PARM_1 + 2)
;     loadRegFromAop (a, SOF(x), 0)
	lda	10,s
;     storeRegToAop (a, EXT(___fseq_PARM_1), 0), stacked=0, isaddr=1
	sta	(___fseq_PARM_1 + 3)
;     genAssign
;     loadRegFromAop (a, LIT(#0x00), 3)
	lda	#0x3F
;     storeRegToAop (a, EXT(___fseq_PARM_2), 3), stacked=0, isaddr=1
	sta	___fseq_PARM_2
;     loadRegFromAop (a, LIT(#0x00), 2)
	lda	#0x80
;     storeRegToAop (a, EXT(___fseq_PARM_2), 2), stacked=0, isaddr=1
	sta	(___fseq_PARM_2 + 1)
;     loadRegFromAop (a, LIT(#0x00), 1)
;     storeRegToAop (a, EXT(___fseq_PARM_2), 1), stacked=0, isaddr=1
;     loadRegFromAop (a, LIT(#0x00), 0)
;     storeRegToAop (a, EXT(___fseq_PARM_2), 0), stacked=0, isaddr=1
; Peephole 5c   - eliminated redundant clra
	clra
	sta	(___fseq_PARM_2 + 2)
	sta	(___fseq_PARM_2 + 3)
;     genCall
	jsr	___fseq
;     loadRegFromAop (a, REG(-,-,-,a), 0)
; transferRegReg(a,a)
;     storeRegToAop (a, REG(-,-,x,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
;     genIfx
	tsta
;     genIfxJump
; Peephole 2d	- eliminated jmp
	beq	00108$
00115$:
; forgot to free a
;     genRet
	clr	*__ret3
	clr	*__ret2
;     loadRegFromAop (x, LIT(#0xDB), 1)
	ldx	#0x0F
;     storeRegToAop (x, REG(-,-,-,x), 0), stacked=0, isaddr=0
; transferRegReg(x,x)
;     loadRegFromAop (a, LIT(#0xDB), 0)
	lda	#0xDB
;     storeRegToAop (a, REG(-,-,-,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
	jmp	00110$
00108$:
;asinf.c:28: else if(x==-1.0) return -HALF_PI;
;     genAssign
;     loadRegFromAop (a, SOF(x), 3)
	lda	7,s
;     storeRegToAop (a, EXT(___fseq_PARM_1), 3), stacked=0, isaddr=1
	sta	___fseq_PARM_1
;     loadRegFromAop (a, SOF(x), 2)
	lda	8,s
;     storeRegToAop (a, EXT(___fseq_PARM_1), 2), stacked=0, isaddr=1
	sta	(___fseq_PARM_1 + 1)
;     loadRegFromAop (a, SOF(x), 1)
	lda	9,s
;     storeRegToAop (a, EXT(___fseq_PARM_1), 1), stacked=0, isaddr=1
	sta	(___fseq_PARM_1 + 2)
;     loadRegFromAop (a, SOF(x), 0)
	lda	10,s
;     storeRegToAop (a, EXT(___fseq_PARM_1), 0), stacked=0, isaddr=1
	sta	(___fseq_PARM_1 + 3)
;     genAssign
;     loadRegFromAop (a, LIT(#0x00), 3)
	lda	#0xBF
;     storeRegToAop (a, EXT(___fseq_PARM_2), 3), stacked=0, isaddr=1
	sta	___fseq_PARM_2
;     loadRegFromAop (a, LIT(#0x00), 2)
	lda	#0x80
;     storeRegToAop (a, EXT(___fseq_PARM_2), 2), stacked=0, isaddr=1
	sta	(___fseq_PARM_2 + 1)
;     loadRegFromAop (a, LIT(#0x00), 1)
;     storeRegToAop (a, EXT(___fseq_PARM_2), 1), stacked=0, isaddr=1
;     loadRegFromAop (a, LIT(#0x00), 0)
;     storeRegToAop (a, EXT(___fseq_PARM_2), 0), stacked=0, isaddr=1
; Peephole 5c   - eliminated redundant clra
	clra
	sta	(___fseq_PARM_2 + 2)
	sta	(___fseq_PARM_2 + 3)
;     genCall
	jsr	___fseq
;     loadRegFromAop (a, REG(-,-,-,a), 0)
; transferRegReg(a,a)
;     storeRegToAop (a, REG(-,-,x,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
;     genIfx
	tsta
;     genIfxJump
; Peephole 2d	- eliminated jmp
	beq	00105$
00116$:
; forgot to free a
;     genRet
	mov	#0xBF,*__ret3
	mov	#0xC9,*__ret2
;     loadRegFromAop (x, LIT(#0xDB), 1)
	ldx	#0x0F
;     storeRegToAop (x, REG(-,-,-,x), 0), stacked=0, isaddr=0
; transferRegReg(x,x)
;     loadRegFromAop (a, LIT(#0xDB), 0)
	lda	#0xDB
;     storeRegToAop (a, REG(-,-,-,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
; Peephole 3	- shortened jmp to bra
	bra	00110$
00105$:
;asinf.c:29: else if(x== 0.0) return 0.0;
;     genIfx
;     loadRegFromAop (a, SOF(x), 0)
	lda	10,s
	ora	9,s
	ora	8,s
	ora	7,s
;     genIfxJump
; Peephole 2c	- eliminated jmp
	bne	00102$
00117$:
;     genRet
	clr	*__ret3
	clr	*__ret2
;     loadRegFromAop (x, LIT(#0x00), 1)
	clrx
;     storeRegToAop (x, REG(-,-,-,x), 0), stacked=0, isaddr=0
; transferRegReg(x,x)
;     loadRegFromAop (a, LIT(#0x00), 0)
	clra
;     storeRegToAop (a, REG(-,-,-,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
; Peephole 3	- shortened jmp to bra
	bra	00110$
00102$:
;asinf.c:30: else return asincosf(x,0);
;     genAssign
;     loadRegFromAop (a, SOF(x), 3)
	lda	7,s
;     storeRegToAop (a, EXT(_asincosf_PARM_1), 3), stacked=0, isaddr=1
	sta	_asincosf_PARM_1
;     loadRegFromAop (a, SOF(x), 2)
	lda	8,s
;     storeRegToAop (a, EXT(_asincosf_PARM_1), 2), stacked=0, isaddr=1
	sta	(_asincosf_PARM_1 + 1)
;     loadRegFromAop (a, SOF(x), 1)
	lda	9,s
;     storeRegToAop (a, EXT(_asincosf_PARM_1), 1), stacked=0, isaddr=1
	sta	(_asincosf_PARM_1 + 2)
;     loadRegFromAop (a, SOF(x), 0)
	lda	10,s
;     storeRegToAop (a, EXT(_asincosf_PARM_1), 0), stacked=0, isaddr=1
	sta	(_asincosf_PARM_1 + 3)
;     genAssign
;     loadRegFromAop (a, LIT(#0x00), 1)
;     storeRegToAop (a, EXT(_asincosf_PARM_2), 1), stacked=0, isaddr=1
;     loadRegFromAop (a, LIT(#0x00), 0)
;     storeRegToAop (a, EXT(_asincosf_PARM_2), 0), stacked=0, isaddr=1
; Peephole 5c   - eliminated redundant clra
	clra
	sta	_asincosf_PARM_2
	sta	(_asincosf_PARM_2 + 1)
;     genCall
	jsr	_asincosf
;     loadRegFromAop (a, REG(-,-,-,a), 0)
; transferRegReg(a,a)
;     storeRegToAop (a, SOF(iTemp2), 0), stacked=0, isaddr=0
	sta	4,s
;     loadRegFromAop (x, REG(-,-,-,x), 0)
; transferRegReg(x,x)
;     storeRegToAop (x, SOF(iTemp2), 1), stacked=0, isaddr=0
	stx	3,s
;     loadRegFromAop (a, DIR(__ret2), 0)
	lda	*__ret2
;     storeRegToAop (a, SOF(iTemp2), 2), stacked=0, isaddr=0
	sta	2,s
;     loadRegFromAop (a, DIR(__ret3), 0)
	lda	*__ret3
;     storeRegToAop (a, SOF(iTemp2), 3), stacked=0, isaddr=0
	sta	1,s
;     genRet
;     loadRegFromAop (a, SOF(iTemp2), 3)
	lda	1,s
;     storeRegToAop (a, DIR(__ret3), 0), stacked=0, isaddr=0
	sta	*__ret3
;     loadRegFromAop (a, SOF(iTemp2), 2)
	lda	2,s
;     storeRegToAop (a, DIR(__ret2), 0), stacked=0, isaddr=0
	sta	*__ret2
;     loadRegFromAop (x, SOF(iTemp2), 1)
	ldx	3,s
;     storeRegToAop (x, REG(-,-,-,x), 0), stacked=0, isaddr=0
; transferRegReg(x,x)
;     loadRegFromAop (a, SOF(iTemp2), 0)
	lda	4,s
;     storeRegToAop (a, REG(-,-,-,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
00110$:
	ais	#4
	rts
	.area CSEG (CODE)
	.area CONST   (CODE)
	.area XINIT
