;--------------------------------------------------------
; File Created by SDCC : FreeWare ANSI-C Compiler
; Version 2.6.1 #4330 (Oct 18 2006)
; This file generated Wed Oct 18 23:31:06 2006
;--------------------------------------------------------
	.module _fslt
	.optsdcc -mhc08
	
	.area HOME (CODE)
	.area GSINIT0 (CODE)
	.area GSINIT (CODE)
	.area GSFINAL (CODE)
	.area CSEG (CODE)
	.area XINIT
	.area CONST   (CODE)
	.area DSEG
	.area OSEG    (OVR)
	.area BSEG
	.area XSEG
	.area XISEG
;--------------------------------------------------------
; Public variables in this module
;--------------------------------------------------------
	.globl ___fslt_PARM_2
	.globl ___fslt_PARM_1
	.globl ___fslt
;--------------------------------------------------------
;  ram data
;--------------------------------------------------------
	.area DSEG
;--------------------------------------------------------
; overlayable items in  ram 
;--------------------------------------------------------
	.area	OSEG    (OVR)
___fslt_sloc0_1_0::
	.ds 4
___fslt_sloc1_1_0::
	.ds 4
;--------------------------------------------------------
; external initialized ram data
;--------------------------------------------------------
	.area XISEG
;--------------------------------------------------------
; extended address mode data
;--------------------------------------------------------
	.area XSEG
___fslt_PARM_1:
	.ds 4
___fslt_PARM_2:
	.ds 4
___fslt_fl1_1_1:
	.ds 4
___fslt_fl2_1_1:
	.ds 4
;--------------------------------------------------------
; global & static initialisations
;--------------------------------------------------------
	.area HOME (CODE)
	.area GSINIT (CODE)
	.area GSFINAL (CODE)
	.area GSINIT (CODE)
;--------------------------------------------------------
; Home
;--------------------------------------------------------
	.area HOME (CODE)
	.area CSEG (CODE)
;--------------------------------------------------------
; code
;--------------------------------------------------------
	.area CSEG (CODE)
;------------------------------------------------------------
;Allocation info for local variables in function '__fslt'
;------------------------------------------------------------
;a1                        Allocated with name '___fslt_PARM_1'
;a2                        Allocated with name '___fslt_PARM_2'
;fl1                       Allocated with name '___fslt_fl1_1_1'
;fl2                       Allocated with name '___fslt_fl2_1_1'
;sloc0                     Allocated with name '___fslt_sloc0_1_0'
;sloc1                     Allocated with name '___fslt_sloc1_1_0'
;------------------------------------------------------------
;_fslt.c:101: char __fslt (float a1, float a2)
;	-----------------------------------------
;	 function __fslt
;	-----------------------------------------
___fslt:
;_fslt.c:105: fl1.f = a1;
;     genPointerSet
;     genDataPointerSet
;     aopDerefAop(IMMD(___fslt_fl1_1_1))
;     loadRegFromAop (a, EXT(___fslt_PARM_1), 3)
	lda	___fslt_PARM_1
;     storeRegToAop (a, EXT(___fslt_fl1_1_1), 3), stacked=0, isaddr=0
	sta	___fslt_fl1_1_1
;     loadRegFromAop (a, EXT(___fslt_PARM_1), 2)
	lda	(___fslt_PARM_1 + 1)
;     storeRegToAop (a, EXT(___fslt_fl1_1_1), 2), stacked=0, isaddr=0
	sta	(___fslt_fl1_1_1 + 1)
;     loadRegFromAop (a, EXT(___fslt_PARM_1), 1)
	lda	(___fslt_PARM_1 + 2)
;     storeRegToAop (a, EXT(___fslt_fl1_1_1), 1), stacked=0, isaddr=0
	sta	(___fslt_fl1_1_1 + 2)
;     loadRegFromAop (a, EXT(___fslt_PARM_1), 0)
	lda	(___fslt_PARM_1 + 3)
;     storeRegToAop (a, EXT(___fslt_fl1_1_1), 0), stacked=0, isaddr=0
	sta	(___fslt_fl1_1_1 + 3)
;_fslt.c:106: fl2.f = a2;
;     genPointerSet
;     genDataPointerSet
;     aopDerefAop(IMMD(___fslt_fl2_1_1))
;     loadRegFromAop (a, EXT(___fslt_PARM_2), 3)
	lda	___fslt_PARM_2
;     storeRegToAop (a, EXT(___fslt_fl2_1_1), 3), stacked=0, isaddr=0
	sta	___fslt_fl2_1_1
;     loadRegFromAop (a, EXT(___fslt_PARM_2), 2)
	lda	(___fslt_PARM_2 + 1)
;     storeRegToAop (a, EXT(___fslt_fl2_1_1), 2), stacked=0, isaddr=0
	sta	(___fslt_fl2_1_1 + 1)
;     loadRegFromAop (a, EXT(___fslt_PARM_2), 1)
	lda	(___fslt_PARM_2 + 2)
;     storeRegToAop (a, EXT(___fslt_fl2_1_1), 1), stacked=0, isaddr=0
	sta	(___fslt_fl2_1_1 + 2)
;     loadRegFromAop (a, EXT(___fslt_PARM_2), 0)
	lda	(___fslt_PARM_2 + 3)
;     storeRegToAop (a, EXT(___fslt_fl2_1_1), 0), stacked=0, isaddr=0
	sta	(___fslt_fl2_1_1 + 3)
;_fslt.c:108: if (fl1.l<0 && fl2.l<0) {
;     genPointerGet
;     genDataPointerGet
;     aopDerefAop(IMMD(___fslt_fl1_1_1))
;     loadRegFromAop (a, EXT(___fslt_fl1_1_1), 3)
	lda	___fslt_fl1_1_1
;     storeRegToAop (a, DIR(___fslt_sloc0_1_0), 3), stacked=0, isaddr=0
	sta	*___fslt_sloc0_1_0
;     loadRegFromAop (a, EXT(___fslt_fl1_1_1), 2)
	lda	(___fslt_fl1_1_1 + 1)
;     storeRegToAop (a, DIR(___fslt_sloc0_1_0), 2), stacked=0, isaddr=0
	sta	*(___fslt_sloc0_1_0 + 1)
;     loadRegFromAop (a, EXT(___fslt_fl1_1_1), 1)
	lda	(___fslt_fl1_1_1 + 2)
;     storeRegToAop (a, DIR(___fslt_sloc0_1_0), 1), stacked=0, isaddr=0
	sta	*(___fslt_sloc0_1_0 + 2)
;     loadRegFromAop (a, EXT(___fslt_fl1_1_1), 0)
	lda	(___fslt_fl1_1_1 + 3)
;     storeRegToAop (a, DIR(___fslt_sloc0_1_0), 0), stacked=0, isaddr=0
	sta	*(___fslt_sloc0_1_0 + 3)
;     genCmp	(<)
;     loadRegFromAop (a, DIR(___fslt_sloc0_1_0), 3)
	lda	*___fslt_sloc0_1_0
	sub	#0x00
	blt	00114$
; Peephole 3	- shortened jmp to bra
	bra	00104$
00114$:
;     genPointerGet
;     genDataPointerGet
;     aopDerefAop(IMMD(___fslt_fl2_1_1))
;     loadRegFromAop (a, EXT(___fslt_fl2_1_1), 3)
	lda	___fslt_fl2_1_1
;     storeRegToAop (a, DIR(___fslt_sloc0_1_0), 3), stacked=0, isaddr=0
	sta	*___fslt_sloc0_1_0
;     loadRegFromAop (a, EXT(___fslt_fl2_1_1), 2)
	lda	(___fslt_fl2_1_1 + 1)
;     storeRegToAop (a, DIR(___fslt_sloc0_1_0), 2), stacked=0, isaddr=0
	sta	*(___fslt_sloc0_1_0 + 1)
;     loadRegFromAop (a, EXT(___fslt_fl2_1_1), 1)
	lda	(___fslt_fl2_1_1 + 2)
;     storeRegToAop (a, DIR(___fslt_sloc0_1_0), 1), stacked=0, isaddr=0
	sta	*(___fslt_sloc0_1_0 + 2)
;     loadRegFromAop (a, EXT(___fslt_fl2_1_1), 0)
	lda	(___fslt_fl2_1_1 + 3)
;     storeRegToAop (a, DIR(___fslt_sloc0_1_0), 0), stacked=0, isaddr=0
	sta	*(___fslt_sloc0_1_0 + 3)
;     genCmp	(<)
;     loadRegFromAop (a, DIR(___fslt_sloc0_1_0), 3)
	lda	*___fslt_sloc0_1_0
	sub	#0x00
; Peephole 2l	- eliminated bra
	bge	00104$
00115$:
;_fslt.c:109: if (fl2.l < fl1.l)
;     genPointerGet
;     genDataPointerGet
;     aopDerefAop(IMMD(___fslt_fl2_1_1))
;     loadRegFromAop (a, EXT(___fslt_fl2_1_1), 3)
	lda	___fslt_fl2_1_1
;     storeRegToAop (a, DIR(___fslt_sloc0_1_0), 3), stacked=0, isaddr=0
	sta	*___fslt_sloc0_1_0
;     loadRegFromAop (a, EXT(___fslt_fl2_1_1), 2)
	lda	(___fslt_fl2_1_1 + 1)
;     storeRegToAop (a, DIR(___fslt_sloc0_1_0), 2), stacked=0, isaddr=0
	sta	*(___fslt_sloc0_1_0 + 1)
;     loadRegFromAop (a, EXT(___fslt_fl2_1_1), 1)
	lda	(___fslt_fl2_1_1 + 2)
;     storeRegToAop (a, DIR(___fslt_sloc0_1_0), 1), stacked=0, isaddr=0
	sta	*(___fslt_sloc0_1_0 + 2)
;     loadRegFromAop (a, EXT(___fslt_fl2_1_1), 0)
	lda	(___fslt_fl2_1_1 + 3)
;     storeRegToAop (a, DIR(___fslt_sloc0_1_0), 0), stacked=0, isaddr=0
	sta	*(___fslt_sloc0_1_0 + 3)
;     genPointerGet
;     genDataPointerGet
;     aopDerefAop(IMMD(___fslt_fl1_1_1))
;     loadRegFromAop (a, EXT(___fslt_fl1_1_1), 3)
	lda	___fslt_fl1_1_1
;     storeRegToAop (a, DIR(___fslt_sloc1_1_0), 3), stacked=0, isaddr=0
	sta	*___fslt_sloc1_1_0
;     loadRegFromAop (a, EXT(___fslt_fl1_1_1), 2)
	lda	(___fslt_fl1_1_1 + 1)
;     storeRegToAop (a, DIR(___fslt_sloc1_1_0), 2), stacked=0, isaddr=0
	sta	*(___fslt_sloc1_1_0 + 1)
;     loadRegFromAop (a, EXT(___fslt_fl1_1_1), 1)
	lda	(___fslt_fl1_1_1 + 2)
;     storeRegToAop (a, DIR(___fslt_sloc1_1_0), 1), stacked=0, isaddr=0
	sta	*(___fslt_sloc1_1_0 + 2)
;     loadRegFromAop (a, EXT(___fslt_fl1_1_1), 0)
	lda	(___fslt_fl1_1_1 + 3)
;     storeRegToAop (a, DIR(___fslt_sloc1_1_0), 0), stacked=0, isaddr=0
	sta	*(___fslt_sloc1_1_0 + 3)
;     genCmp	(<)
;     loadRegFromAop (a, DIR(___fslt_sloc0_1_0), 0)
	lda	*(___fslt_sloc0_1_0 + 3)
	sub	*(___fslt_sloc1_1_0 + 3)
;     loadRegFromAop (a, DIR(___fslt_sloc0_1_0), 1)
	lda	*(___fslt_sloc0_1_0 + 2)
	sbc	*(___fslt_sloc1_1_0 + 2)
;     loadRegFromAop (a, DIR(___fslt_sloc0_1_0), 2)
	lda	*(___fslt_sloc0_1_0 + 1)
	sbc	*(___fslt_sloc1_1_0 + 1)
;     loadRegFromAop (a, DIR(___fslt_sloc0_1_0), 3)
	lda	*___fslt_sloc0_1_0
	sbc	*___fslt_sloc1_1_0
; Peephole 2l	- eliminated bra
	bge	00102$
00116$:
;_fslt.c:110: return (1);
;     genRet
;     loadRegFromAop (a, LIT(#0x01), 0)
	lda	#0x01
;     storeRegToAop (a, REG(-,-,-,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
; Peephole 3	- shortened jmp to bra
; Peephole 6b  - replaced jmp to rts with rts
	rts
00102$:
;_fslt.c:111: return (0);
;     genRet
;     loadRegFromAop (a, LIT(#0x00), 0)
	clra
;     storeRegToAop (a, REG(-,-,-,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
; Peephole 3	- shortened jmp to bra
; Peephole 6b  - replaced jmp to rts with rts
	rts
00104$:
;_fslt.c:114: if (fl1.l < fl2.l)
;     genPointerGet
;     genDataPointerGet
;     aopDerefAop(IMMD(___fslt_fl1_1_1))
;     loadRegFromAop (a, EXT(___fslt_fl1_1_1), 3)
	lda	___fslt_fl1_1_1
;     storeRegToAop (a, DIR(___fslt_sloc1_1_0), 3), stacked=0, isaddr=0
	sta	*___fslt_sloc1_1_0
;     loadRegFromAop (a, EXT(___fslt_fl1_1_1), 2)
	lda	(___fslt_fl1_1_1 + 1)
;     storeRegToAop (a, DIR(___fslt_sloc1_1_0), 2), stacked=0, isaddr=0
	sta	*(___fslt_sloc1_1_0 + 1)
;     loadRegFromAop (a, EXT(___fslt_fl1_1_1), 1)
	lda	(___fslt_fl1_1_1 + 2)
;     storeRegToAop (a, DIR(___fslt_sloc1_1_0), 1), stacked=0, isaddr=0
	sta	*(___fslt_sloc1_1_0 + 2)
;     loadRegFromAop (a, EXT(___fslt_fl1_1_1), 0)
	lda	(___fslt_fl1_1_1 + 3)
;     storeRegToAop (a, DIR(___fslt_sloc1_1_0), 0), stacked=0, isaddr=0
	sta	*(___fslt_sloc1_1_0 + 3)
;     genPointerGet
;     genDataPointerGet
;     aopDerefAop(IMMD(___fslt_fl2_1_1))
;     loadRegFromAop (a, EXT(___fslt_fl2_1_1), 3)
	lda	___fslt_fl2_1_1
;     storeRegToAop (a, DIR(___fslt_sloc0_1_0), 3), stacked=0, isaddr=0
	sta	*___fslt_sloc0_1_0
;     loadRegFromAop (a, EXT(___fslt_fl2_1_1), 2)
	lda	(___fslt_fl2_1_1 + 1)
;     storeRegToAop (a, DIR(___fslt_sloc0_1_0), 2), stacked=0, isaddr=0
	sta	*(___fslt_sloc0_1_0 + 1)
;     loadRegFromAop (a, EXT(___fslt_fl2_1_1), 1)
	lda	(___fslt_fl2_1_1 + 2)
;     storeRegToAop (a, DIR(___fslt_sloc0_1_0), 1), stacked=0, isaddr=0
	sta	*(___fslt_sloc0_1_0 + 2)
;     loadRegFromAop (a, EXT(___fslt_fl2_1_1), 0)
	lda	(___fslt_fl2_1_1 + 3)
;     storeRegToAop (a, DIR(___fslt_sloc0_1_0), 0), stacked=0, isaddr=0
	sta	*(___fslt_sloc0_1_0 + 3)
;     genCmp	(<)
;     loadRegFromAop (a, DIR(___fslt_sloc1_1_0), 0)
	lda	*(___fslt_sloc1_1_0 + 3)
	sub	*(___fslt_sloc0_1_0 + 3)
;     loadRegFromAop (a, DIR(___fslt_sloc1_1_0), 1)
	lda	*(___fslt_sloc1_1_0 + 2)
	sbc	*(___fslt_sloc0_1_0 + 2)
;     loadRegFromAop (a, DIR(___fslt_sloc1_1_0), 2)
	lda	*(___fslt_sloc1_1_0 + 1)
	sbc	*(___fslt_sloc0_1_0 + 1)
;     loadRegFromAop (a, DIR(___fslt_sloc1_1_0), 3)
	lda	*___fslt_sloc1_1_0
	sbc	*___fslt_sloc0_1_0
; Peephole 2l	- eliminated bra
	bge	00107$
00117$:
;_fslt.c:115: return (1);
;     genRet
;     loadRegFromAop (a, LIT(#0x01), 0)
	lda	#0x01
;     storeRegToAop (a, REG(-,-,-,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
; Peephole 3	- shortened jmp to bra
; Peephole 6b  - replaced jmp to rts with rts
	rts
00107$:
;_fslt.c:116: return (0);
;     genRet
;     loadRegFromAop (a, LIT(#0x00), 0)
	clra
;     storeRegToAop (a, REG(-,-,-,a), 0), stacked=0, isaddr=0
; transferRegReg(a,a)
00108$:
	rts
	.area CSEG (CODE)
	.area CONST   (CODE)
	.area XINIT
